diff options
| author | Simon Glass <sjg@chromium.org> | 2016-01-17 16:11:55 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:09:42 +0800 |
| commit | 278d3a4444cd89214be7951d7493716990361b7b (patch) | |
| tree | 9cd5f02168c168107911badd5d801df59f186e9b /arch/x86/cpu/ivybridge/usb_ehci.c | |
| parent | 1605b10032eb073b6854fdeddbf455bf403eb6f1 (diff) | |
| download | talos-obmc-uboot-278d3a4444cd89214be7951d7493716990361b7b.tar.gz talos-obmc-uboot-278d3a4444cd89214be7951d7493716990361b7b.zip | |
x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge/usb_ehci.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/usb_ehci.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c deleted file mode 100644 index da11aee94d..0000000000 --- a/arch/x86/cpu/ivybridge/usb_ehci.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -void bd82x6x_usb_ehci_init(pci_dev_t dev) -{ - u32 reg32; - - /* Disable Wake on Disconnect in RMH */ - reg32 = readl(RCB_REG(0x35b0)); - reg32 |= 0x22; - writel(reg32, RCB_REG(0x35b0)); - - debug("EHCI: Setting up controller.. "); - reg32 = x86_pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - /* reg32 |= PCI_COMMAND_SERR; */ - x86_pci_write_config32(dev, PCI_COMMAND, reg32); - - debug("done.\n"); -} |
