diff options
| author | Simon Glass <sjg@chromium.org> | 2014-11-12 22:42:07 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:34:11 +0100 |
| commit | 8ef07571a0300e6ae84931c63d5eb3b2310c8aba (patch) | |
| tree | 609c66ebe81b00690783e881a28c1bfb266670c2 /arch/x86/cpu/ivybridge/car.S | |
| parent | c03c951b065f2b9f98caf913192a41a8f8200fd4 (diff) | |
| download | talos-obmc-uboot-8ef07571a0300e6ae84931c63d5eb3b2310c8aba.tar.gz talos-obmc-uboot-8ef07571a0300e6ae84931c63d5eb3b2310c8aba.zip | |
x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge/car.S')
| -rw-r--r-- | arch/x86/cpu/ivybridge/car.S | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S new file mode 100644 index 0000000000..0480813b74 --- /dev/null +++ b/arch/x86/cpu/ivybridge/car.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> + + /* Note: ebp must not be touched in this code */ +.globl car_init +car_init: + /* TODO: Add cache-as-RAM init here */ + jmp car_init_ret |
