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author | Simon Glass <sjg@chromium.org> | 2016-03-16 07:44:36 -0600 |
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committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:27 +0800 |
commit | 7e4a6ae62c7ee567ae43e94445e561b3ec8343b9 (patch) | |
tree | 6fb33d50aa6943375f844432bfe3b6a1921ba9b7 /arch/x86/cpu/intel_common/pch.c | |
parent | f215287bd59c28443efe6118e7e958be733ce727 (diff) | |
download | talos-obmc-uboot-7e4a6ae62c7ee567ae43e94445e561b3ec8343b9.tar.gz talos-obmc-uboot-7e4a6ae62c7ee567ae43e94445e561b3ec8343b9.zip |
x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/intel_common/pch.c')
-rw-r--r-- | arch/x86/cpu/intel_common/pch.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c new file mode 100644 index 0000000000..1f05b44586 --- /dev/null +++ b/arch/x86/cpu/intel_common/pch.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <asm/pch_common.h> + +u32 pch_common_sir_read(struct udevice *dev, int idx) +{ + u32 data; + + dm_pci_write_config32(dev, SATA_SIRI, idx); + dm_pci_read_config32(dev, SATA_SIRD, &data); + + return data; +} + +void pch_common_sir_write(struct udevice *dev, int idx, u32 value) +{ + dm_pci_write_config32(dev, SATA_SIRI, idx); + dm_pci_write_config32(dev, SATA_SIRD, value); +} |