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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:26 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:29 -0500 |
| commit | a1d558a20f1eaeae9927abc4e0978725d33bae53 (patch) | |
| tree | 3af577ebb7be24efd3c23d7a8559512d2f9bfa70 /arch/powerpc/include | |
| parent | eb5394120643922626f18e5fe7b0b3dc0ed43b9a (diff) | |
| download | talos-obmc-uboot-a1d558a20f1eaeae9927abc4e0978725d33bae53.tar.gz talos-obmc-uboot-a1d558a20f1eaeae9927abc4e0978725d33bae53.zip | |
powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ecb156619d..92ca2ad74d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -512,6 +512,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 +#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_B4860) |
