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| author | Tang Yuantian <yuantian.tang@freescale.com> | 2014-07-04 17:39:26 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-07-22 16:25:55 -0700 |
| commit | 7cb7272365983e3a1eedf18a9f688c825e1cf95e (patch) | |
| tree | 5ce567157d236767a0f05940045bf6f8c3c27ca3 /arch/powerpc/include/asm | |
| parent | a1399a918720337ad14053cf6185786aa33b58b2 (diff) | |
| download | talos-obmc-uboot-7cb7272365983e3a1eedf18a9f688c825e1cf95e.tar.gz talos-obmc-uboot-7cb7272365983e3a1eedf18a9f688c825e1cf95e.zip | |
mpc85xx/t104x: Enable L2 and CPC cache when resume
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/cache.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index cdc1f10872..d3a83910b6 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -57,6 +57,12 @@ extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +int l2cache_init(void); +void enable_cpc(void); +void disable_cpc_sram(void); +#endif + /* prep registers for L2 */ #define CACHECRBA 0x80000823 /* Cache configuration register address */ #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ |
