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| author | Stefan Roese <sr@denx.de> | 2010-07-21 11:08:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-07-23 09:54:28 +0200 |
| commit | b995d7cb2c1e47305cd7feb2513ed37d30f8edd3 (patch) | |
| tree | 67ece77e91c2b489ccbdd53000a7a4d33176e623 /arch/powerpc/include/asm/ppc4xx-sdram.h | |
| parent | 897d6abc50e95fb57fa6952c27deae5776ba08cc (diff) | |
| download | talos-obmc-uboot-b995d7cb2c1e47305cd7feb2513ed37d30f8edd3.tar.gz talos-obmc-uboot-b995d7cb2c1e47305cd7feb2513ed37d30f8edd3.zip | |
ppc4xx: DDR/ECC: Use correct macros to clear error status
Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.
Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/include/asm/ppc4xx-sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx-sdram.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 42eac4531f..4ec1ef866a 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -63,6 +63,8 @@ #define SDRAM_CFG0 0x20 /* memory controller options 0 */ #define SDRAM_CFG1 0x21 /* memory controller options 1 */ +#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */ +#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */ #define SDRAM0_BEAR 0x0010 /* bus error address reg */ #define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */ #define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */ |
