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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:22 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:26 -0500 |
| commit | 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 (patch) | |
| tree | 4bf4bebd73d19138e8f726112ba0c41cbde94a15 /arch/powerpc/include/asm/fsl_ddr_sdram.h | |
| parent | 111fd19e3b9eb1005fd24ef09c163dd10103f5fa (diff) | |
| download | talos-obmc-uboot-57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2.tar.gz talos-obmc-uboot-57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2.zip | |
powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.
CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
000 -> Termsel off
001 -> 120 Ohm
010 -> 180 Ohm
011 -> 75 Ohm
100 -> 110 Ohm
101 -> 60 Ohm
110 -> 70 Ohm
111 -> 47 Ohm
Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.
Extend DDR register timing_cfg_1 to have 4 bits for each field.
DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_ddr_sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index e271342f08..9cf9bd4a2a 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -145,6 +145,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { @@ -177,6 +202,8 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; @@ -262,6 +289,8 @@ typedef struct memctl_options_s { unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; unsigned int twoT_en; @@ -288,6 +317,7 @@ typedef struct memctl_options_s { unsigned int rcw_2; /* control register 1 */ unsigned int ddr_cdr1; + unsigned int ddr_cdr2; unsigned int trwt_override; unsigned int trwt; /* read-to-write turnaround */ |
