powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support

- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

1 files changed, 13 insertions, 1 deletions

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 191629b628..83dd739b5c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -505,6 +505,18 @@
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
+#elif defined(CONFIG_BSC9131)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
 #else
 #error Processor type not defined for this platform
 #endif