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| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:41 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:38 -0700 |
| commit | cb93071bb6da21d17dd7d7d414a389b380f959b2 (patch) | |
| tree | ef8cc19e0c01b00baeda237802d4b6b383d5e5f7 /arch/powerpc/cpu/mpc8xxx | |
| parent | 7adefb55adf3e55f3788c3b9682ba91d29da2595 (diff) | |
| download | talos-obmc-uboot-cb93071bb6da21d17dd7d7d414a389b380f959b2.tar.gz talos-obmc-uboot-cb93071bb6da21d17dd7d7d414a389b380f959b2.zip | |
mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index ff5812df55..0f73e9c6c6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1638,5 +1638,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_rcw(ddr, popts, common_dimm); +#ifdef CONFIG_SYS_FSL_DDR_EMU + /* disble DDR training for emulator */ + ddr->debug[2] = 0x00000400; + ddr->debug[4] = 0xff800000; +#endif return check_fsl_memctl_config_regs(ddr); } |
