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| author | Yangbo Lu <yangbo.lu@freescale.com> | 2015-04-22 13:57:40 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:25:39 -0700 |
| commit | 2d9ca2c72c0fce33052f78f02cdc8ad0a5cf4292 (patch) | |
| tree | 5f175881751b0f63276b58adc59e07cdc5ef3ca8 /arch/powerpc/cpu/mpc85xx | |
| parent | b46cf1b178c7e79240dd8ddb700b3394afbb4192 (diff) | |
| download | talos-obmc-uboot-2d9ca2c72c0fce33052f78f02cdc8ad0a5cf4292.tar.gz talos-obmc-uboot-2d9ca2c72c0fce33052f78f02cdc8ad0a5cf4292.zip | |
mmc: fsl_esdhc: Add peripheral clock support
The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 321ade24fe..d954fe2fd2 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -73,7 +73,8 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ + defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -453,6 +454,48 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_PPC_T2080) +#define ESDHC_CLK_SEL 0x00000007 +#define ESDHC_CLK_SHIFT 0 +#define ESDHC_CLK_RCWSR 15 +#else /* Support T1040 T1024 by now */ +#define ESDHC_CLK_SEL 0xe0000000 +#define ESDHC_CLK_SHIFT 29 +#define ESDHC_CLK_RCWSR 7 +#endif + rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); + switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { + case 1: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; + break; + case 2: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; + break; + case 3: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; + break; +#if defined(CONFIG_SYS_SDHC_CLK_2_PLL) + case 4: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; + break; +#if defined(CONFIG_PPC_T2080) + case 5: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; + break; +#endif + case 6: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; + break; + case 7: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; + break; +#endif + default: + sys_info->freq_sdhc = 0; + printf("Error: Unknown SDHC peripheral clock select!\n"); + } +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { @@ -660,12 +703,16 @@ int get_clocks (void) gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; +#else #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ defined(CONFIG_P1014) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; #endif +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) |
