diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:30 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:32 -0500 |
| commit | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 (patch) | |
| tree | 7d648c2c312b9cc7a75c0350101aacc67afca399 /arch/powerpc/cpu/mpc85xx/tlb.c | |
| parent | 3f0997b3255c1498ac92453aa3a7a1cc95914dfd (diff) | |
| download | talos-obmc-uboot-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.gz talos-obmc-uboot-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.zip | |
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/tlb.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/tlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 929f6a607e..a548dec9a7 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -249,7 +249,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; - unsigned int wimge = 0; + unsigned int wimge = MAS2_M; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam; u64 size, memsize = (u64)memsize_in_meg << 20; |
