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| author | York Sun <yorksun@freescale.com> | 2013-03-25 07:40:07 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 16:54:11 -0500 |
| commit | f69814397e7efaf0b2bfa3c83425c906ce6b50f4 (patch) | |
| tree | 3526ce4f78bb8d70ad0e0b80df23002a5ee5fb07 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 5f208d118a8590843aaca723d304b35f2729c141 (diff) | |
| download | talos-obmc-uboot-f69814397e7efaf0b2bfa3c83425c906ce6b50f4.tar.gz talos-obmc-uboot-f69814397e7efaf0b2bfa3c83425c906ce6b50f4.zip | |
powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.
Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.
Cluster clock registers are reorganized to be easily indexed.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 41 |
1 files changed, 19 insertions, 22 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 467ea1045d..a4a21b037c 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -154,16 +154,12 @@ __secondary_start_page: ori r3,r3,toreset(__spin_table_addr)@l lwz r3,0(r3) - /* - * r10 has the base address for the entry. - * we cannot access it yet before setting up a new TLB - */ mfspr r0,SPRN_PIR #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * PIR definition for Chassis 2 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID, 2'b00 - SoC 1 + * 18-19 CHIP_ID, 2'b00 - SoC 1 * all others - reserved * 20-24 CLUSTER_ID 5'b00000 - CCM 1 * all others - reserved @@ -177,32 +173,33 @@ __secondary_start_page: * 2'b11 - core 3 * 29-31 THREAD_ID 3'b000 - thread 0 * 3'b001 - thread 1 + * + * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08 + * and clusters by 0x20. + * + * We renumber PIR so that all threads in the system are consecutive. */ - rlwinm r4,r0,29,25,31 + + rlwinm r8,r0,29,0x03 /* r8 = core within cluster */ + srwi r10,r0,5 /* r10 = cluster */ + + mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER + add r5,r5,r8 /* for spin table index */ + mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */ #elif defined(CONFIG_E500MC) rlwinm r4,r0,27,27,31 + mr r5,r4 #else mr r4,r0 + mr r5,r4 #endif - slwi r8,r4,6 /* spin table is padded to 64 byte */ - add r10,r3,r8 -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 - mfspr r0,SPRN_PIR /* - * core 0 thread 0: pir reset value 0x00, new pir 0 - * core 0 thread 1: pir reset value 0x01, new pir 1 - * core 1 thread 0: pir reset value 0x08, new pir 2 - * core 1 thread 1: pir reset value 0x09, new pir 3 - * core 2 thread 0: pir reset value 0x10, new pir 4 - * core 2 thread 1: pir reset value 0x11, new pir 5 - * etc. - * - * Only thread 0 of each core will be running, updating PIR doesn't - * need to deal with the thread bits. + * r10 has the base address for the entry. + * we cannot access it yet before setting up a new TLB */ - rlwinm r4,r0,30,24,30 -#endif + slwi r8,r5,6 /* spin table is padded to 64 byte */ + add r10,r3,r8 mtspr SPRN_PIR,r4 /* write to PIR register */ |
