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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-07-21 00:20:21 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-07-29 08:53:38 -0500 |
| commit | acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 (patch) | |
| tree | 85681bacc33dff6bfcd9f40ad2e93c9635dc4ba1 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | db564bccefaa537b4a2bd46778b00536bab17258 (diff) | |
| download | talos-obmc-uboot-acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72.tar.gz talos-obmc-uboot-acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72.zip | |
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853ee57..6678ed4118 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 |
