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| author | Scott Wood <scottwood@freescale.com> | 2012-08-14 10:14:53 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 12:16:54 -0500 |
| commit | 33eee330cc8a445ff05f39a58af3c87324798230 (patch) | |
| tree | 183b1fd72ce4cdd395aa009ea739602a992df56c /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 3e978f5dc85db40432f73380aa5be53096205f18 (diff) | |
| download | talos-obmc-uboot-33eee330cc8a445ff05f39a58af3c87324798230.tar.gz talos-obmc-uboot-33eee330cc8a445ff05f39a58af3c87324798230.zip | |
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 1555a9ba67..043d0ff773 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -74,6 +74,33 @@ __secondary_start_page: mtspr 977,r3 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xff + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + cmpw r3,r4 + beq 1f + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + cmpw r3,r4 + beq 1f +#endif + + /* Not a supported revision affected by erratum */ + b 2f + +1: /* Erratum says set bits 55:60 to 001001 */ + msync + isync + mfspr r3,976 + li r4,0x48 + rlwimi r3,r4,0,0x1f8 + mtspr 976,r3 + isync +2: +#endif + /* Enable branch prediction */ lis r3,BUCSR_ENABLE@h ori r3,r3,BUCSR_ENABLE@l |
