diff options
| author | York Sun <yorksun@freescale.com> | 2015-08-17 13:31:52 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-09-01 20:42:54 -0500 |
| commit | 2becdc6f9df470b6c768d59509e661d1066b38c7 (patch) | |
| tree | e59d49b8c3e661e07a50ca475ad17a3030735cf4 /arch/powerpc/cpu/mpc85xx/p3041_ids.c | |
| parent | b3142e2cf82ab207a88868264d709a40e83f065e (diff) | |
| download | talos-obmc-uboot-2becdc6f9df470b6c768d59509e661d1066b38c7.tar.gz talos-obmc-uboot-2becdc6f9df470b6c768d59509e661d1066b38c7.zip | |
powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/p3041_ids.c')
0 files changed, 0 insertions, 0 deletions
