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| author | Timur Tabi <timur@freescale.com> | 2011-08-05 16:15:24 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-09-29 19:01:05 -0500 |
| commit | fbb9ecf7493fbd6b8c8af7d52e90c915459f7040 (patch) | |
| tree | b19bce4d9c77be58fc1aba43bd73625222c99f8f /arch/powerpc/cpu/mpc85xx/cpu.c | |
| parent | 86df5142a14868ea0e24511f4293d43a611a2b39 (diff) | |
| download | talos-obmc-uboot-fbb9ecf7493fbd6b8c8af7d52e90c915459f7040.tar.gz talos-obmc-uboot-fbb9ecf7493fbd6b8c8af7d52e90c915459f7040.zip | |
powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 22fa4615cb..f51829e0fe 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -64,7 +64,8 @@ int checkcpu (void) u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ - int i; + unsigned int i, core, nr_cores = cpu_numcores(); + u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); @@ -119,11 +120,11 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:"); - for (i = 0; i < cpu_numcores(); i++) { + for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); - printf("CPU%d:%-4s MHz, ", - i,strmhz(buf1, sysinfo.freqProcessor[i])); + printf("CPU%d:%-4s MHz, ", core, + strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); |
