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| author | Anatolij Gustschin <agust@denx.de> | 2013-02-08 00:03:49 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2013-03-09 08:23:02 +0100 |
| commit | a615dfda8c2041dd98ecd238d45f3bc35e495b44 (patch) | |
| tree | b177e8e05649ba7da7f8f7dcfe309fb29b7aef68 /arch/powerpc/cpu/mpc512x | |
| parent | fcc7fe425183f9ec95fba33d041eb359d0a3a598 (diff) | |
| download | talos-obmc-uboot-a615dfda8c2041dd98ecd238d45f3bc35e495b44.tar.gz talos-obmc-uboot-a615dfda8c2041dd98ecd238d45f3bc35e495b44.zip | |
mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/mpc512x')
| -rw-r--r-- | arch/powerpc/cpu/mpc512x/fixed_sdram.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c index 550cbd0bd6..6635fb036e 100644 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c @@ -99,7 +99,19 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, sync_law(&im->sysconf.ddrlaw.ar); /* DDR Enable */ - out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); + /* + * the "enable" combination: DRAM controller out of reset, + * clock enabled, command mode -- BUT leave CKE low for now + */ + i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); + /* maintain 200 microseconds of stable power and clock */ + udelay(200); + /* apply a NOP, it shouldn't harm */ + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP); + /* now assert CKE (high) */ + i |= MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -148,6 +160,9 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); + /* Allow for the DLL to startup before accessing data */ + udelay(10); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE); /* Fix DDR Local Window for new size */ out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1); |
