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| author | Zhi-zhou Zhang <etou.zh@gmail.com> | 2012-10-16 15:02:08 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2012-10-16 15:02:08 +0200 |
| commit | cb0a6a1ecc8dfe4dbdad6f9376ef78879337b118 (patch) | |
| tree | 6398daa7ee7188509950120a9377bfa91e9c478c /arch/mips/include/asm | |
| parent | bd23b22badadcdc414a900828253961fc5ec6c39 (diff) | |
| download | talos-obmc-uboot-cb0a6a1ecc8dfe4dbdad6f9376ef78879337b118.tar.gz talos-obmc-uboot-cb0a6a1ecc8dfe4dbdad6f9376ef78879337b118.zip | |
MIPS: don't use camel-case style
Replace camel-case style with upper-case style globally.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/asm.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 82 |
2 files changed, 42 insertions, 42 deletions
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcfbb3..933ccb1b78 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -401,7 +401,7 @@ symbol = value #ifdef CONFIG_SGI_IP28 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ #include <asm/cacheops.h> -#define R10KCBARRIER(addr) cache Cache_Barrier, addr; +#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr; #else #define R10KCBARRIER(addr) #endif diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 70bcad7694..6464250d84 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -14,54 +14,54 @@ /* * Cache Operations available on all MIPS processors with R4000-style caches */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 +#define INDEX_INVALIDATE_I 0x00 +#define INDEX_WRITEBACK_INV_D 0x01 +#define INDEX_LOAD_TAG_I 0x04 +#define INDEX_LOAD_TAG_D 0x05 +#define INDEX_STORE_TAG_I 0x08 +#define INDEX_STORE_TAG_D 0x09 #if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 +#define HIT_INVALIDATE_I 0x00 #else -#define Hit_Invalidate_I 0x10 +#define HIT_INVALIDATE_I 0x10 #endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 +#define HIT_INVALIDATE_D 0x11 +#define HIT_WRITEBACK_INV_D 0x15 /* * R4000-specific cacheops */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define CREATE_DIRTY_EXCL_D 0x0d +#define FILL 0x14 +#define HIT_WRITEBACK_I 0x18 +#define HIT_WRITEBACK_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define INDEX_INVALIDATE_SI 0x02 +#define INDEX_WRITEBACK_INV_SD 0x03 +#define INDEX_LOAD_TAG_SI 0x06 +#define INDEX_LOAD_TAG_SD 0x07 +#define INDEX_STORE_TAG_SI 0x0A +#define INDEX_STORE_TAG_SD 0x0B +#define CREATE_DIRTY_EXCL_SD 0x0f +#define HIT_INVALIDATE_SI 0x12 +#define HIT_INVALIDATE_SD 0x13 +#define HIT_WRITEBACK_INV_SD 0x17 +#define HIT_WRITEBACK_SD 0x1b +#define HIT_SET_VIRTUAL_SI 0x1e +#define HIT_SET_VIRTUAL_SD 0x1f /* * R5000-specific cacheops */ -#define R5K_Page_Invalidate_S 0x17 +#define R5K_PAGE_INVALIDATE_S 0x17 /* * RM7000-specific cacheops */ -#define Page_Invalidate_T 0x16 +#define PAGE_INVALIDATE_T 0x16 /* * R10000-specific cacheops @@ -69,17 +69,17 @@ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f +#define INDEX_WRITEBACK_INV_S 0x03 +#define INDEX_LOAD_TAG_S 0x07 +#define INDEX_STORE_TAG_S 0x0B +#define HIT_INVALIDATE_S 0x13 +#define CACHE_BARRIER 0x14 +#define HIT_WRITEBACK_INV_S 0x17 +#define INDEX_LOAD_DATA_I 0x18 +#define INDEX_LOAD_DATA_D 0x19 +#define INDEX_LOAD_DATA_S 0x1b +#define INDEX_STORE_DATA_I 0x1c +#define INDEX_STORE_DATA_D 0x1d +#define INDEX_STORE_DATA_S 0x1f #endif /* __ASM_CACHEOPS_H */ |
