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author | Anton Staaf <robotboy@chromium.org> | 2011-10-17 16:46:11 -0700 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-10-23 20:50:43 +0200 |
commit | 72d4dd4159c4f3978c20c04f78fe6aa02450da1a (patch) | |
tree | aac2196572eacdc26dbd97ba9b9ac3343a1cb1c6 /arch/mips/include/asm | |
parent | ee729afde3a4782e1ef57962afd13fb7208f5cb8 (diff) | |
download | talos-obmc-uboot-72d4dd4159c4f3978c20c04f78fe6aa02450da1a.tar.gz talos-obmc-uboot-72d4dd4159c4f3978c20c04f78fe6aa02450da1a.zip |
mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r-- | arch/mips/include/asm/cache.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h new file mode 100644 index 0000000000..5406d5d46a --- /dev/null +++ b/arch/mips/include/asm/cache.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MIPS_CACHE_H__ +#define __MIPS_CACHE_H__ + +/* + * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use + * that as a default for aligning DMA buffers unless the board config has + * specified another cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 128 +#endif + +#endif /* __MIPS_CACHE_H__ */ |