blackfin: bf60x: new processor header files

Add header files for blackfin new processor bf60x.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>

13 files changed, 1090 insertions, 1 deletions

diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
index a19f0f74e6..86087117ef 100644
--- a/arch/blackfin/include/asm/blackfin_cdef.h
+++ b/arch/blackfin/include/asm/blackfin_cdef.h
@@ -84,5 +84,8 @@
 #ifdef __ADSPBF561__
 # include "mach-bf561/BF561_cdef.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_cdef.h"
+#endif
 
 #endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
index f06d1f12cc..c96a3ecbba 100644
--- a/arch/blackfin/include/asm/blackfin_def.h
+++ b/arch/blackfin/include/asm/blackfin_def.h
@@ -136,5 +136,10 @@
 # include "mach-bf561/anomaly.h"
 # include "mach-bf561/def_local.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_def.h"
+# include "mach-bf609/anomaly.h"
+# include "mach-bf609/def_local.h"
+#endif
 
 #endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 49d0c9ec3a..fc46ef4d11 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -61,6 +61,9 @@
 extern u_long get_vco(void);
 extern u_long get_cclk(void);
 extern u_long get_sclk(void);
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
 
 # define bfin_revid() (bfin_read_CHIPID() >> 28)
 
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
new file mode 100644
index 0000000000..c5900319f2
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
@@ -0,0 +1,192 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF609_proc__
+#define __BFIN_CDEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT)
+#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL)
+#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL)
+#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val)
+#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV)
+#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val)
+
+#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
+#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
+
+#define bfin_read_CHIPID()		bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
+
+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
+
+#define bfin_read_SEC_CCTL()		bfin_read32(SEC0_CCTL0)
+#define bfin_write_SEC_CCTL(val)	bfin_write32(SEC0_CCTL0, val)
+#define bfin_read_SEC_GCTL()		bfin_read32(SEC0_GCTL)
+#define bfin_write_SEC_GCTL(val)	bfin_write32(SEC0_GCTL, val)
+
+#define bfin_read_SEC_FCTL()		bfin_read32(SEC0_FCTL)
+#define bfin_write_SEC_FCTL(val)	bfin_write32(SEC0_FCTL, val)
+#define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC0_SCTL0 + (sid) * 8))
+#define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC0_SCTL0 \
+	+ (sid) * 8), val)
+
+#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
+#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
+#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
+#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
+#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
+#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
+#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
+#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
+#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
+#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
+#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
+#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
+#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
+#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
+#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
+#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
+#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
+#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
+#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
+#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
+#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
+#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
+#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
+#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
+#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
+#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
+#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
+
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLL_OSC)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
+#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read8(USB_DMA_IRQ)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
+#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
+
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val)
+#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val)
+#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG)
+#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val)
+#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT)
+#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val)
+#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val)
+#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT)
+#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val)
+#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val)
+#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val)
+#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val)
+
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK)
+#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val)
+
+#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
+#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
+#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val)
+#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
+#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
+#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
+#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val)
+#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
+
+#define bfin_read_RSI_CLK_CONTROL()    bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CONTROL()   bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUSCL()       bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUSCL(val)   bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CONTROL()  bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_BLKSZ()          bfin_read16(RSI_BLKSZ)
+#define bfin_write_RSI_BLKSZ(val)      bfin_write16(RSI_BLKSZ, val)
+#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_ESTAT()          bfin_read32(RSI_ESTAT)
+#define bfin_write_RSI_ESTAT(val)      bfin_write32(RSI_ESTAT, val)
+#define bfin_read_RSI_EMASK()          bfin_read32(RSI_EMASK)
+#define bfin_write_RSI_EMASK(val)      bfin_write32(RSI_EMASK, val)
+#define bfin_read_RSI_CONFIG()         bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CONFIG(val)     bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
new file mode 100644
index 0000000000..8c1dcd006e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
@@ -0,0 +1,247 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF609_proc__
+#define __BFIN_DEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define RSI_CLK_CONTROL   0xFFC00604 /* RSI0 Clock Control Register */
+#define RSI_ARGUMENT      0xFFC00608 /* RSI0 Argument Register */
+#define RSI_COMMAND       0xFFC0060C /* RSI0 Command Register */
+#define RSI_RESP_CMD      0xFFC00610 /* RSI0 Response Command Register */
+#define RSI_RESPONSE0     0xFFC00614 /* RSI0 Response 0 Register */
+#define RSI_RESPONSE1     0xFFC00618 /* RSI0 Response 1 Register */
+#define RSI_RESPONSE2     0xFFC0061C /* RSI0 Response 2 Register */
+#define RSI_RESPONSE3     0xFFC00620 /* RSI0 Response 3 Register */
+#define RSI_DATA_TIMER    0xFFC00624 /* RSI0 Data Timer Register */
+#define RSI_DATA_LGTH     0xFFC00628 /* RSI0 Data Length Register */
+#define RSI_DATA_CONTROL  0xFFC0062C /* RSI0 Data Control Register */
+#define RSI_DATA_CNT      0xFFC00630 /* RSI0 Data Count Register */
+#define RSI_STATUS        0xFFC00634 /* RSI0 Status Register */
+#define RSI_STATUSCL      0xFFC00638 /* RSI0 Status Clear Register */
+#define RSI_IMSK0         0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
+#define RSI_IMSK1         0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT      0xFFC00648 /* RSI0 FIFO Counter Register */
+#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */
+#define RSI_BOOT_TCNTR    0xFFC00650 /* RSI0 Boot Timing Counter Register */
+#define RSI_BACK_TOUT     0xFFC00654 /* RSI0 Boot Ack Timeout Register */
+#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
+#define RSI_BLKSZ         0xFFC0065C /* RSI0 Block Size Register */
+#define RSI_FIFO          0xFFC00680 /* RSI0 Data FIFO Register */
+#define RSI_ESTAT         0xFFC006C0 /* RSI0 Exception Status Register */
+#define RSI_EMASK         0xFFC006C4 /* RSI0 Exception Mask Register */
+#define RSI_CONFIG        0xFFC006C8 /* RSI0 Configuration Register */
+#define RSI_RD_WAIT_EN    0xFFC006CC /* RSI0 Read Wait Enable Register */
+#define RSI_PID0          0xFFC006D0 /* RSI0 Peripheral Id Register */
+#define RSI_PID1          0xFFC006D4 /* RSI0 Peripheral Id Register */
+#define RSI_PID2          0xFFC006D8 /* RSI0 Peripheral Id Register */
+#define RSI_PID3          0xFFC006DC /* RSI0 Peripheral Id Register */
+
+#define TWI0_CLKDIV       0xFFC01E00 /* TWI0 SCL Clock Divider */
+#define TWI1_CLKDIV       0xFFC01F00 /* TWI1 SCL Clock Divider */
+
+#define UART0_REVID       0xFFC02000 /* UART0 Revision ID Register */
+#define UART0_CTL         0xFFC02004 /* UART0 Control Register */
+#define UART0_STAT        0xFFC02008 /* UART0 Status Register */
+#define UART0_SCR         0xFFC0200C /* UART0 Scratch Register */
+#define UART0_CLK         0xFFC02010 /* UART0 Clock Rate Register */
+#define UART0_IMSK        0xFFC02014 /* UART0 Interrupt Mask Register */
+#define UART0_IMSK_SET    0xFFC02018 /* UART0 Interrupt Mask Set Register */
+#define UART0_IMSK_CLR    0xFFC0201C /* UART0 Interrupt Mask Clear Register */
+#define UART0_RBR         0xFFC02020 /* UART0 Receive Buffer Register */
+#define UART0_THR         0xFFC02024 /* UART0 Transmit Hold Register */
+#define UART0_TAIP        0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */
+#define UART0_TSR         0xFFC0202C /* UART0 Transmit Shift Register */
+#define UART0_RSR         0xFFC02030 /* UART0 Receive Shift Register */
+#define UART0_TXCNT       0xFFC02034 /* UART0 Transmit Counter Register */
+#define UART0_RXCNT       0xFFC02038 /* UART0 Receive Counter Register */
+#define UART1_REVID       0xFFC02400 /* UART1 Revision ID Register */
+#define UART1_CTL         0xFFC02404 /* UART1 Control Register */
+#define UART1_STAT        0xFFC02408 /* UART1 Status Register */
+#define UART1_SCR         0xFFC0240C /* UART1 Scratch Register */
+#define UART1_CLK         0xFFC02410 /* UART1 Clock Rate Register */
+#define UART1_IMSK        0xFFC02414 /* UART1 Interrupt Mask Register */
+#define UART1_IMSK_SET    0xFFC02418 /* UART1 Interrupt Mask Set Register */
+#define UART1_IMSK_CLR    0xFFC0241C /* UART1 Interrupt Mask Clear Register */
+#define UART1_RBR         0xFFC02420 /* UART1 Receive Buffer Register */
+#define UART1_THR         0xFFC02424 /* UART1 Transmit Hold Register */
+#define UART1_TAIP        0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */
+#define UART1_TSR         0xFFC0242C /* UART1 Transmit Shift Register */
+#define UART1_RSR         0xFFC02430 /* UART1 Receive Shift Register */
+#define UART1_TXCNT       0xFFC02434 /* UART1 Transmit Counter Register */
+#define UART1_RXCNT       0xFFC02438 /* UART1 Receive Counter Register */
+
+#define PORTA_FER         0xFFC03000 /* PORTA Port x Function Enable */
+#define PORTA_FER_SET     0xFFC03004 /* PORTA Port x Function Enable Set */
+#define PORTA_FER_CLR     0xFFC03008 /* PORTA Port x Function Enable Clear */
+#define PORTA_MUX         0xFFC03030 /* PORTA Port x Multiplexer Control */
+#define PORTB_FER         0xFFC03080 /* PORTB Port x Function Enable */
+#define PORTB_FER_SET     0xFFC03084 /* PORTB Port x Function Enable Set */
+#define PORTB_FER_CLR     0xFFC03088 /* PORTB Port x Function Enable Clear */
+#define PORTB_MUX         0xFFC030B0 /* PORTB Port x Multiplexer Control */
+#define PORTC_FER         0xFFC03100 /* PORTC Port x Function Enable */
+#define PORTC_FER_SET     0xFFC03104 /* PORTC Port x Function Enable Set */
+#define PORTC_FER_CLR     0xFFC03108 /* PORTC Port x Function Enable Clear */
+#define PORTC_MUX         0xFFC03130 /* PORTC Port x Multiplexer Control */
+#define PORTD_FER         0xFFC03180 /* PORTD Port x Function Enable */
+#define PORTD_FER_SET     0xFFC03184 /* PORTD Port x Function Enable Set */
+#define PORTD_FER_CLR     0xFFC03188 /* PORTD Port x Function Enable Clear */
+#define PORTD_MUX         0xFFC031B0 /* PORTD Port x Multiplexer Control */
+#define PORTE_FER         0xFFC03200 /* PORTE Port x Function Enable */
+#define PORTE_FER_SET     0xFFC03204 /* PORTE Port x Function Enable Set */
+#define PORTE_FER_CLR     0xFFC03208 /* PORTE Port x Function Enable Clear */
+#define PORTE_MUX         0xFFC03230 /* PORTE Port x Multiplexer Control */
+#define PORTF_FER         0xFFC03280 /* PORTF Port x Function Enable */
+#define PORTF_FER_SET     0xFFC03284 /* PORTF Port x Function Enable Set */
+#define PORTF_FER_CLR     0xFFC03288 /* PORTF Port x Function Enable Clear */
+#define PORTF_MUX         0xFFC032B0 /* PORTF Port x Multiplexer Control */
+#define PORTG_FER         0xFFC03300 /* PORTG Port x Function Enable */
+#define PORTG_FER_SET     0xFFC03304 /* PORTG Port x Function Enable Set */
+#define PORTG_FER_CLR     0xFFC03308 /* PORTG Port x Function Enable Clear */
+#define PORTG_MUX         0xFFC03330 /* PORTG Port x Multiplexer Control */
+
+#define SMC_GCTL          0xFFC16004 /* SMC Control Register */
+#define SMC_GSTAT         0xFFC16008 /* SMC Status Register */
+#define SMC_B0CTL         0xFFC1600C /* SMC Bank0 Control Register */
+#define SMC_B0TIM         0xFFC16010 /* SMC Bank0 Timing Register */
+#define SMC_B0ETIM        0xFFC16014 /* SMC Bank0 Extended Timing Register */
+#define SMC_B1CTL         0xFFC1601C /* SMC BANK1 Control Register */
+#define SMC_B1TIM         0xFFC16020 /* SMC BANK1 Timing Register */
+#define SMC_B1ETIM        0xFFC16024 /* SMC BANK1 Extended Timing Register */
+#define SMC_B2CTL         0xFFC1602C /* SMC BANK2 Control Register */
+#define SMC_B2TIM         0xFFC16030 /* SMC BANK2 Timing Register */
+#define SMC_B2ETIM        0xFFC16034 /* SMC BANK2 Extended Timing Register */
+#define SMC_B3CTL         0xFFC1603C /* SMC BANK3 Control Register */
+#define SMC_B3TIM         0xFFC16040 /* SMC BANK3 Timing Register */
+#define SMC_B3ETIM        0xFFC16044 /* SMC BANK3 Extended Timing Register */
+
+#define WDOG_CTL          0xFFC17000 /* WDOG0 Control Register */
+#define WDOG_CNT          0xFFC17004 /* WDOG0 Count Register */
+#define WDOG_STAT         0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
+#define WDOG1_CTL         0xFFC17800 /* WDOG1 Control Register */
+#define WDOG1_CNT         0xFFC17804 /* WDOG1 Count Register */
+#define WDOG1_STAT        0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
+
+#define EMAC0_MACCFG      0xFFC20000 /* EMAC0 MAC Configuration Register */
+#define EMAC1_MACCFG      0xFFC22000 /* EMAC1 MAC Configuration Register */
+
+#define DMA10_DSCPTR_NXT  0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
+#define DMA10_ADDRSTART   0xFFC05004 /* DMA10 Start Address of Current Buf */
+#define DMA10_CFG         0xFFC05008 /* DMA10 Configuration Register */
+#define DMA10_XCNT        0xFFC0500C /* DMA10 Inner Loop Count Start Value */
+#define DMA10_XMOD        0xFFC05010 /* DMA10 Inner Loop Address Increment */
+#define DMA10_YCNT        0xFFC05014 /* DMA10 Outer Loop Count Start Value */
+#define DMA10_YMOD        0xFFC05018 /* DMA10 Outer Loop Address Increment */
+#define DMA10_DSCPTR_CUR  0xFFC05024 /* DMA10 Current Descriptor Pointer */
+#define DMA10_DSCPTR_PRV  0xFFC05028 /* DMA10 Previous Initial Desc Pointer */
+#define DMA10_ADDR_CUR    0xFFC0502C /* DMA10 Current Address */
+#define DMA10_STAT        0xFFC05030 /* DMA10 Status Register */
+#define DMA10_XCNT_CUR    0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/
+#define DMA10_YCNT_CUR    0xFFC05038 /* DMA10 Curr Row Count (2D only) */
+#define DMA10_BWLCNT      0xFFC05040 /* DMA10 Bandwidth Limit Count */
+#define DMA10_BWLCNT_CUR  0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
+#define DMA10_BWMCNT      0xFFC05048 /* DMA10 Bandwidth Monitor Count */
+#define DMA10_BWMCNT_CUR  0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/
+
+#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
+#define DMA21_DSCPTR_NXT  0xFFC09000 /* DMA21 Pointer to Next Initial Desc */
+#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
+#define DMA22_DSCPTR_NXT  0xFFC09080 /* DMA22 Pointer to Next Initial Desc */
+
+#define DMC0_ID           0xFFC80000 /* DMC0 Identification Register */
+#define DMC0_CTL          0xFFC80004 /* DMC0 Control Register */
+#define DMC0_STAT         0xFFC80008 /* DMC0 Status Register */
+#define DMC0_EFFCTL       0xFFC8000C /* DMC0 Efficiency Controller */
+#define DMC0_PRIO         0xFFC80010 /* DMC0 Priority ID Register */
+#define DMC0_PRIOMSK      0xFFC80014 /* DMC0 Priority ID Mask */
+#define DMC0_CFG          0xFFC80040 /* DMC0 SDRAM Configuration */
+#define DMC0_TR0          0xFFC80044 /* DMC0 Timing Register 0 */
+#define DMC0_TR1          0xFFC80048 /* DMC0 Timing Register 1 */
+#define DMC0_TR2          0xFFC8004C /* DMC0 Timing Register 2 */
+#define DMC0_MSK          0xFFC8005C /* DMC0 Mode Register Mask */
+#define DMC0_MR           0xFFC80060 /* DMC0 Mode Shadow register */
+#define DMC0_EMR1         0xFFC80064 /* DMC0 EMR1 Shadow Register */
+#define DMC0_EMR2         0xFFC80068 /* DMC0 EMR2 Shadow Register */
+#define DMC0_EMR3         0xFFC8006C /* DMC0 EMR3 Shadow Register */
+#define DMC0_DLLCTL       0xFFC80080 /* DMC0 DLL Control Register */
+#define DMC0_PADCTL       0xFFC800C0 /* DMC0 PAD Control Register 0 */
+
+#define SEC0_CCTL0        0xFFCA4400 /* SEC0 Core Control Register n */
+#define SEC0_CCTL1        0xFFCA4440 /* SEC0 Core Control Register n */
+#define SEC0_FCTL         0xFFCA4010 /* SEC0 Fault Control Register */
+#define SEC0_GCTL         0xFFCA4000 /* SEC0 Global Control Register */
+#define SEC0_SCTL0        0xFFCA4800 /* SEC0 IRQ Source Control Register n */
+
+#define RCU0_CTL          0xFFCA6000 /* RCU0 Control Register */
+#define RCU0_STAT         0xFFCA6004 /* RCU0 Status Register */
+#define RCU0_CRCTL        0xFFCA6008 /* RCU0 Core Reset Control Register */
+#define RCU0_CRSTAT       0xFFCA600C /* RCU0 Core Reset Status Register */
+#define RCU0_SIDIS        0xFFCA6010 /* RCU0 Sys Interface Disable Register */
+#define RCU0_SISTAT       0xFFCA6014 /* RCU0 Sys Interface Status Register */
+#define RCU0_SVECT_LCK    0xFFCA6018 /* RCU0 SVECT Lock Register */
+#define RCU0_BCODE        0xFFCA601C /* RCU0 Boot Code Register */
+#define RCU0_SVECT0       0xFFCA6020 /* RCU0 Software Vector Register n */
+#define RCU0_SVECT1       0xFFCA6024 /* RCU0 Software Vector Register n */
+
+#define CGU_CTL           0xFFCA8000 /* CGU0 Control Register */
+#define CGU_STAT          0xFFCA8004 /* CGU0 Status Register */
+#define CGU_DIV           0xFFCA8008 /* CGU0 Divisor Register */
+#define CGU_CLKOUTSEL     0xFFCA800C /* CGU0 CLKOUT Select Register */
+
+#define DPM0_CTL          0xFFCA9000 /* DPM0 Control Register */
+#define DPM0_STAT         0xFFCA9004 /* DPM0 Status Register */
+#define DPM0_CCBF_DIS     0xFFCA9008 /* DPM0 Core Clock Buffer Disable */
+#define DPM0_CCBF_EN      0xFFCA900C /* DPM0 Core Clock Buffer Enable */
+#define DPM0_CCBF_STAT    0xFFCA9010 /* DPM0 Core Clock Buffer Status */
+#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */
+#define DPM0_SCBF_DIS     0xFFCA9018 /* DPM0 System Clock Buffer Disable */
+#define DPM0_WAKE_EN      0xFFCA901C /* DPM0 Wakeup Enable Register */
+#define DPM0_WAKE_POL     0xFFCA9020 /* DPM0 Wakeup Polarity Register */
+#define DPM0_WAKE_STAT    0xFFCA9024 /* DPM0 Wakeup Status Register */
+#define DPM0_HIB_DIS      0xFFCA9028 /* DPM0 Hibernate Disable Register */
+#define DPM0_PGCNTR       0xFFCA902C /* DPM0 Power Good Counter Register */
+#define DPM0_RESTORE0     0xFFCA9030 /* DPM0 Restore Register */
+#define DPM0_RESTORE1     0xFFCA9034 /* DPM0 Restore Register */
+#define DPM0_RESTORE2     0xFFCA9038 /* DPM0 Restore Register */
+#define DPM0_RESTORE3     0xFFCA903C /* DPM0 Restore Register */
+#define DPM0_RESTORE4     0xFFCA9040 /* DPM0 Restore Register */
+#define DPM0_RESTORE5     0xFFCA9044 /* DPM0 Restore Register */
+#define DPM0_RESTORE6     0xFFCA9048 /* DPM0 Restore Register */
+#define DPM0_RESTORE7     0xFFCA904C /* DPM0 Restore Register */
+#define DPM0_RESTORE8     0xFFCA9050 /* DPM0 Restore Register */
+#define DPM0_RESTORE9     0xFFCA9054 /* DPM0 Restore Register */
+#define DPM0_RESTORE10    0xFFCA9058 /* DPM0 Restore Register */
+#define DPM0_RESTORE11    0xFFCA905C /* DPM0 Restore Register */
+#define DPM0_RESTORE12    0xFFCA9060 /* DPM0 Restore Register */
+#define DPM0_RESTORE13    0xFFCA9064 /* DPM0 Restore Register */
+#define DPM0_RESTORE14    0xFFCA9068 /* DPM0 Restore Register */
+#define DPM0_RESTORE15    0xFFCA906C /* DPM0 Restore Register */
+
+#define USB_FADDR         0xFFCC1000 /* USB Device Address in Peripheral Mode*/
+#define USB_DMA_IRQ       0xFFCC1200 /* USB Interrupt Register */
+#define USB_VBUS_CTL      0xFFCC1380 /* USB VBus Control */
+#define USB_PHY_CTL       0xFFCC1394 /* USB PHY Control */
+#define USB_PLL_OSC       0xFFCC1398 /* USB PLL and Oscillator Control */
+
+
+#define                           CHIPID  0xffc00014
+/* CHIPID Masks */
+#define                   CHIPID_VERSION  0xF0000000
+#define                    CHIPID_FAMILY  0x0FFFF000
+#define               CHIPID_MANUFACTURE  0x00000FFE
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE 0x8000
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE 0x4000
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */
+#define L1_INST_SRAM_SIZE 0x8000
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/anomaly.h b/arch/blackfin/include/asm/mach-bf609/anomaly.h
new file mode 100644
index 0000000000..0a70f082af
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/anomaly.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2004-2012 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
+ */
+
+#if __SILICON_REVISION__ < 0
+# error will not work on BF609 silicon version
+#endif
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_16000010 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000480 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h
new file mode 100644
index 0000000000..d4250e6f99
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/def_local.h
@@ -0,0 +1,5 @@
+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define CONFIG_BF60x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h
new file mode 100644
index 0000000000..757570f2ef
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/portmux.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
+
+/* EMAC RMII Port Mux */
+#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+
+#define P_RMII0 {\
+	P_MII0_ETxD0, \
+	P_MII0_ETxD1, \
+	P_MII0_ETxEN, \
+	P_MII0_ERxD0, \
+	P_MII0_ERxD1, \
+	P_MII0_ERxER, \
+	P_MII0_TxCLK, \
+	P_MII0_PHYINT, \
+	P_MII0_CRS, \
+	P_MII0_MDC, \
+	P_PTP0_PPS, \
+	P_PTP1_PPS, \
+	P_MII0_MDIO, 0}
+
+#define P_MII1_MDC	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_MII1_MDIO	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_MII1_ETxD0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_MII1_ERxD0	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII1_ETxD1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_MII1_ERxD1	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_MII1_ETxEN	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_MII1_PHYINT	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_MII1_CRS	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_MII1_ERxER	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_MII1_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+
+#define P_RMII1 {\
+	P_MII1_ETxD0, \
+	P_MII1_ETxD1, \
+	P_MII1_ETxEN, \
+	P_MII1_ERxD0, \
+	P_MII1_ERxD1, \
+	P_MII1_ERxER, \
+	P_MII1_TxCLK, \
+	P_MII1_PHYINT, \
+	P_MII1_CRS, \
+	P_MII1_MDC, \
+	P_MII1_MDIO, 0}
+
+/* PPI Port Mux */
+#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define P_PPI0_D16	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_PPI0_D17	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_PPI0_D18	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_PPI0_D19	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_PPI0_D20	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_PPI0_D21	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_PPI0_D22	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_PPI0_D23	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
+#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
+#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+
+#define P_PPI1_D0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
+#define P_PPI1_D1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_PPI1_D2	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
+#define P_PPI1_D3	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
+#define P_PPI1_D4	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
+#define P_PPI1_D5	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+#define P_PPI1_D6	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
+#define P_PPI1_D7	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
+#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
+#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
+#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
+#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
+#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
+#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
+#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
+#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
+#define P_PPI1_D16	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_PPI1_D17	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_PPI1_CLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
+#define P_PPI1_FS1	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
+#define P_PPI1_FS2	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_PPI1_FS3	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
+
+#define P_PPI2_D0	(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
+#define P_PPI2_D1	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_PPI2_D2	(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
+#define P_PPI2_D3	(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
+#define P_PPI2_D4	(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
+#define P_PPI2_D5	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_PPI2_D6	(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
+#define P_PPI2_D7	(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
+#define P_PPI2_D8	(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
+#define P_PPI2_D9	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_PPI2_D10	(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
+#define P_PPI2_D11	(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
+#define P_PPI2_D12	(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
+#define P_PPI2_D13	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+#define P_PPI2_D14	(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
+#define P_PPI2_D15	(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
+#define P_PPI2_D16	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
+#define P_PPI2_D17	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_PPI2_CLK	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
+#define P_PPI2_FS1	(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
+#define P_PPI2_FS2	(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
+#define P_PPI2_FS3	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_SPI0_RDY	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_SPI0_D2	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_SPI0_D3	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
+#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+
+#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_SPI1_RDY	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI1_D2	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI1_D3	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+
+#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_SPI1_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI1_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS
+#define P_DEFAULT_BOOT_SPI_CS
+
+/* UART Port Mux */
+#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+
+#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+
+/* Timer */
+#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
+#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
+#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+
+/* RSI */
+#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
+#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
+#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
+#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
+#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
+#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+
+/* PTP */
+#define P_PTP0_PPS	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
+#define P_PTP0_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP0_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+#define P_PTP1_PPS	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_PTP1_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP1_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+/* SMC Port Mux */
+#define P_A3		(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_A4		(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_A5		(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_A6		(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_A7		(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_A8		(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_A9		(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_A10		(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_A11		(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_A12		(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_A13		(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_A14		(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_A15		(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_A16		(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_A17		(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_A18		(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_A19		(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_A20		(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_A21		(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_A22		(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_A23		(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_A24		(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_A25		(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_NORCK         (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+
+#define P_AMS1		(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_AMS2		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_AMS3		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+
+#define P_ABE0		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
+#define P_ABE1		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
+
+/* CAN */
+#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+
+#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h
new file mode 100644
index 0000000000..b361c7bcbe
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/ports.h
@@ -0,0 +1,103 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x00000003
+#define PORT_x_MUX_1_MASK	0x0000000C
+#define PORT_x_MUX_2_MASK	0x00000030
+#define PORT_x_MUX_3_MASK	0x000000C0
+#define PORT_x_MUX_4_MASK	0x00000300
+#define PORT_x_MUX_5_MASK	0x00000C00
+#define PORT_x_MUX_6_MASK	0x00003000
+#define PORT_x_MUX_7_MASK	0x0000C000
+#define PORT_x_MUX_8_MASK	0x00030000
+#define PORT_x_MUX_9_MASK	0x000C0000
+#define PORT_x_MUX_10_MASK	0x00300000
+#define PORT_x_MUX_11_MASK	0x00C00000
+#define PORT_x_MUX_12_MASK	0x03000000
+#define PORT_x_MUX_13_MASK	0x0C000000
+#define PORT_x_MUX_14_MASK	0x30000000
+#define PORT_x_MUX_15_MASK	0xC0000000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
+
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h
new file mode 100644
index 0000000000..cdf7349925
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/cgu.h
@@ -0,0 +1,80 @@
+/*
+ * CGU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_CGU__
+#define __BFIN_PERIPHERAL_CGU__
+
+/* CGU_CTL Masks */
+#define DF			(1 << 0)
+#define MSEL			(0x7f << MSEL_P)
+#define WIDLE			(1 << WIDLE_P)
+#define LOCK			(1 << LOCK_P)
+
+#define DF_P			0
+#define MSEL_P			8
+#define WIDLE_P			30
+#define LOCK_P			31
+#define MSEL_MASK               0x7F00
+#define DF_MASK                 0x1
+
+/* CGU_STAT Masks */
+#define PLLEN			(1 << 0)
+#define PLLBP			(1 << 1)
+#define PLLLK			(1 << 2)
+#define CLKSALGN		(1 << 3)
+#define CCBF0EN			(1 << 4)
+#define CCBF1EN			(1 << 5)
+#define SCBF0EN			(1 << 6)
+#define SCBF1EN			(1 << 7)
+#define DCBFEN			(1 << 8)
+#define OCBFEN			(1 << 9)
+#define ADRERR			(1 << 16)
+#define LWERR			(1 << 17)
+#define DIVERR			(1 << 18)
+#define WDFMSERR		(1 << 19)
+#define WDIVERR			(1 << 20)
+#define PLLLKERR		(1 << 21)
+
+/* CGU_DIV Masks */
+#define CSEL			(0x1f << CSEL_P)
+#define S0SEL			(3 << S0SEL_P)
+#define SYSSEL			(0x1f << SYSSEL_P)
+#define S1SEL			(3 << S1SEL_P)
+#define DSEL			(0x1f << DSEL_P)
+#define OSEL			(0x7f << OSEL_P)
+#define ALGN			(1 << ALGN_P)
+#define UPDT			(1 << UPDT_P)
+#define LOCK			(1 << LOCK_P)
+
+#define CSEL_P			0
+#define S0SEL_P			5
+#define SYSSEL_P		8
+#define S1SEL_P			13
+#define DSEL_P			16
+#define OSEL_P			22
+#define ALGN_P			29
+#define UPDT_P			30
+#define LOCK_P			31
+
+/* CGU_CLKOUTSEL Masks */
+#define CLKOUTSEL		(0xf << 0)
+#define USBCLKSEL		(0x3f << 16)
+#define LOCK			(1 << LOCK_P)
+
+#define LOCK_P			31
+
+#define CLKOUTSEL_CLKIN		0x0
+#define CLKOUTSEL_CCLK		0x1
+#define CLKOUTSEL_SYSCLK	0x2
+#define CLKOUTSEL_SCLK0		0x3
+#define CLKOUTSEL_SCLK1		0x4
+#define CLKOUTSEL_DCLK		0x5
+#define CLKOUTSEL_USB_PLL	0x6
+#define CLKOUTSEL_OUTCLK	0x7
+#define CLKOUTSEL_USB_CLKIN	0x8
+#define CLKOUTSEL_WDOG		0x9
+#define CLKOUTSEL_PMON		0xA
+#define CLKOUTSEL_GND		0xB
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h
new file mode 100644
index 0000000000..f7b0bb90f3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/dde.h
@@ -0,0 +1,88 @@
+/*
+ * Distributed DMA Engine (DDE) Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_DDE__
+#define __BFIN_PERIPHERAL_DDE__
+
+/* DMA_CONFIG Masks */
+#define DMAEN			(1 << DMAEN_P)	/* DMA Channel Enable */
+#define WNR			(1 << WNR_P)	/* Channel Direction (W/R*) */
+#define SYNC			(1 << SYNC_P)	/* Sync Work Unit Transitions */
+#define CADDR			(1 << CADDR_P)	/* Use Current Address */
+#define PSIZE			(7 << PSIZE_P)	/* Peripheral Word Size */
+#define PSIZE_1			(0 << PSIZE_P)
+#define PSIZE_2			(1 << PSIZE_P)
+#define PSIZE_4			(2 << PSIZE_P)
+#define PSIZE_8			(3 << PSIZE_P)
+#define MSIZE			(7 << MSIZE_P)	/* Memory Transfer Size */
+#define MSIZE_1			(0 << MSIZE_P)
+#define MSIZE_2			(1 << MSIZE_P)
+#define MSIZE_4			(2 << MSIZE_P)
+#define MSIZE_8			(3 << MSIZE_P)
+#define MSIZE_16		(4 << MSIZE_P)
+#define MSIZE_32		(5 << MSIZE_P)
+#define FLOW			(7 << FLOW_P)	/* Next Operation */
+#define FLOW_STOP		(0 << FLOW_P)	/* Stop Mode */
+#define FLOW_AUTO		(1 << FLOW_P)	/* Autobuffer Mode */
+#define FLOW_DSCL		(4 << FLOW_P)	/* Descriptor List */
+#define FLOW_DSCA		(5 << FLOW_P)	/* Descriptor Array */
+#define FLOW_DSDL		(6 << FLOW_P)	/* Descriptor On Demand List */
+#define FLOW_DSDA		(7 << FLOW_P)	/* Descriptor On Demand Array */
+#define NDSIZE			(7 << NDSIZE_P)	/* Next Descriptor Set Size */
+#define NDSIZE_1		(0 << NDSIZE_P)
+#define NDSIZE_2		(1 << NDSIZE_P)
+#define NDSIZE_3		(2 << NDSIZE_P)
+#define NDSIZE_4		(3 << NDSIZE_P)
+#define NDSIZE_5		(4 << NDSIZE_P)
+#define NDSIZE_6		(5 << NDSIZE_P)
+#define NDSIZE_7		(6 << NDSIZE_P)
+#define DI_EN_X                 (1 << INT_P)
+#define DI_EN_Y                 (2 << INT_P)
+#define DI_EN_P			(3 << INT_P)
+#define DI_EN			(DI_EN_X)
+#define DI_XCOUNT_EN            (1 << INT_P)    /* xcount expires interrupt */
+#define TRIG			(3 << TRIG_P)	/* Generate Trigger */
+#define TOVEN			(1 << TOVEN_P)
+#define DESCIDCPY		(1 << DESCIDCPY_P)
+#define TWOD			(1 << TWOD_P)
+#define PDRF			(1 << PDRF_P)
+
+#define DMAEN_P			0
+#define WNR_P			1
+#define SYNC_P			2
+#define CADDR_P			3
+#define PSIZE_P			4
+#define MSIZE_P			8
+#define FLOW_P			12
+#define TWAIT_P			15
+#define NDSIZE_P		16
+#define INT_P			20
+#define TRIG_P			22
+#define TOVEN_P			24
+#define DESCIDCPY_P		25
+#define TWOD_P			26
+#define PDRF_P			28
+
+/* DMA_STATUS Masks */
+#define DMA_DONE		(1 << DMA_DONE_P)	/* Work Unit/Row Done */
+#define DMA_ERR			(1 << DMA_ERR_P)	/* Error Interrupt */
+#define DMA_PIRQ		(1 << DMA_PIRQ_P)	/* Peri Intr Request */
+#define DMA_ERRC		(7 << DMA_ERRC_P)	/* Error Cause */
+#define DMA_RUN			(7 << DMA_RUN_P)	/* Run Status */
+#define DMA_PBWIDTH		(3 << DMA_PBWIDTH_P)	/* Peri Bus Width */
+#define DMA_MBWIDTH		(3 << DMA_MBWIDTH_P)	/* Memory Bus Width */
+#define DMA_FIFOFILL		(7 << DMA_FIFOFILL_P)	/* FIFO Fill Status */
+#define DMA_TWAIT		(1 << DMA_TWAIT_P)	/* Trigger Wait Stat */
+
+#define DMA_DONE_P		0
+#define DMA_ERR_P		1
+#define DMA_PIRQ_P		2
+#define DMA_ERRC_P		4
+#define DMA_RUN_P		8
+#define DMA_PBWIDTH_P		12
+#define DMA_MBWIDTH_P		14
+#define DMA_FIFOFILL_P		16
+#define DMA_TWAIT_P		20
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
index 39998f82aa..cfde2364d7 100644
--- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
+++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h
@@ -70,7 +70,11 @@
 #define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
 #define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
 #define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
-#define PAGE_SIZE_MASK		0x00030000	/* the bits for the page_size field */
+#define PAGE_SIZE_16KB		0x00040000	/* 16 KB page size */
+#define PAGE_SIZE_64KB		0x00050000	/* 64 KB page size */
+#define PAGE_SIZE_16MB		0x00060000	/* 16 MB page size */
+#define PAGE_SIZE_64MB		0x00070000	/* 64 MB page size */
+#define PAGE_SIZE_MASK		0x00070000	/* page_size field mask */
 #define PAGE_SIZE_SHIFT		16
 #define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
 #define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
index 9009f26401..fe0ba0f543 100644
--- a/arch/blackfin/include/asm/mach-common/bits/pll.h
+++ b/arch/blackfin/include/asm/mach-common/bits/pll.h
@@ -16,6 +16,8 @@
 #define MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
 #define SPORT_HYST		0x8000		/* Enable Additional Hysteresis on SPORT Input Pins */
 
+#define MSEL_P			9
+
 /* PLL_DIV Masks */
 #define SSEL			0x000F		/* System Select */
 #define CSEL			0x0030		/* Core Select */
@@ -29,6 +31,9 @@
 #define CCLK_DIV4		CSEL_DIV4
 #define CCLK_DIV8		CSEL_DIV8
 
+#define SSEL_P			0
+#define CSEL_P			4
+
 /* PLL_STAT Masks */
 #define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
 #define FULL_ON			0x0002		/* Processor In Full On Mode */