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| author | Sonic Zhang <sonic.zhang@analog.com> | 2013-02-05 18:57:49 +0800 |
|---|---|---|
| committer | Sonic Zhang <sonic.zhang@analog.com> | 2013-05-13 15:47:24 +0800 |
| commit | f4d8038439fb372c91c3a27121a911c359603bcf (patch) | |
| tree | c9a576f2f81d7ad65d8222f20f5c4a1fc4fa0e24 /arch/blackfin/include | |
| parent | ddb5c5be1eddd38a47dc197cfacdbf149930740d (diff) | |
| download | talos-obmc-uboot-f4d8038439fb372c91c3a27121a911c359603bcf.tar.gz talos-obmc-uboot-f4d8038439fb372c91c3a27121a911c359603bcf.zip | |
blackfin: run core1 from L1 code sram start address in uboot init code on core 0
Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Diffstat (limited to 'arch/blackfin/include')
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf561/BF561_def.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf609/BF609_def.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index a7ff5a3feb..8fd552f2a1 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -714,4 +714,6 @@ #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF561_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 8c1dcd006e..4d3b003409 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -244,4 +244,6 @@ #define L1_INST_SRAM_SIZE 0x8000 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF609_proc__ */ |
