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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-11 20:17:45 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-25 00:27:52 +0900 |
| commit | 9879842c6fdb64d95085ac66647ed77d7abfd439 (patch) | |
| tree | d8a28b56fd229cf7991c30bfc0a64abd1c736618 /arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c | |
| parent | 1386233da33235a68d9f4321e505bfa97370d949 (diff) | |
| download | talos-obmc-uboot-9879842c6fdb64d95085ac66647ed77d7abfd439.tar.gz talos-obmc-uboot-9879842c6fdb64d95085ac66647ed77d7abfd439.zip | |
ARM: uniphier: drop DCC micro support card support
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards. It has been painful to maintain
both. Having one of them is enough.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c')
| -rw-r--r-- | arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c deleted file mode 100644 index 877ba79f68..0000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/io.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> - -void sbc_init(void) -{ - /* XECS0: boot/sub memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); - - /* XECS1: sub/boot memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); - - /* XECS3: peripherals */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); - - writel(0x0000bc01, SBBASE0); /* boot memory */ - writel(0x0400bc01, SBBASE1); /* sub memory */ - writel(0x0800bf01, SBBASE3); /* peripherals */ - - /* enable access to sub memory when boot swap is on */ - if (boot_is_swapped()) - sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ - - sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ - writel(0x00000001, SG_LOADPINCTRL); -} |
