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author | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
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committer | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
commit | 9b5b60a05cb8bba2d135439419b2030764e359bd (patch) | |
tree | 15e249ac39e9c547668327218e63a0faf54a3283 /arch/arm/mach-uniphier/memconf.c | |
parent | 32df39c741788e8637cffe6633d73594b26d70fb (diff) | |
parent | 7ae8350f67eea861280a4cbd2d067777a0e87153 (diff) | |
download | talos-obmc-uboot-9b5b60a05cb8bba2d135439419b2030764e359bd.tar.gz talos-obmc-uboot-9b5b60a05cb8bba2d135439419b2030764e359bd.zip |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/mach-uniphier/memconf.c')
-rw-r--r-- | arch/arm/mach-uniphier/memconf.c | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c new file mode 100644 index 0000000000..bf3c177ed9 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +void memconf_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); +} |