ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 0 insertions, 103 deletions

diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
deleted file mode 100644
index 59ed0b5dd8..0000000000
--- a/arch/arm/mach-uniphier/memconf.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
-{
-	int size_mb = size / num;
-	u32 ret;
-
-	switch (size_mb) {
-	case SZ_64M:
-		ret = SG_MEMCONF_CH0_SZ_64M;
-		break;
-	case SZ_128M:
-		ret = SG_MEMCONF_CH0_SZ_128M;
-		break;
-	case SZ_256M:
-		ret = SG_MEMCONF_CH0_SZ_256M;
-		break;
-	case SZ_512M:
-		ret = SG_MEMCONF_CH0_SZ_512M;
-		break;
-	case SZ_1G:
-		ret = SG_MEMCONF_CH0_SZ_1G;
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	switch (num) {
-	case 1:
-		ret |= SG_MEMCONF_CH0_NUM_1;
-		break;
-	case 2:
-		ret |= SG_MEMCONF_CH0_NUM_2;
-		break;
-	default:
-		BUG();
-		break;
-	}
-	return ret;
-}
-
-static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
-{
-	int size_mb = size / num;
-	u32 ret;
-
-	switch (size_mb) {
-	case SZ_64M:
-		ret = SG_MEMCONF_CH1_SZ_64M;
-		break;
-	case SZ_128M:
-		ret = SG_MEMCONF_CH1_SZ_128M;
-		break;
-	case SZ_256M:
-		ret = SG_MEMCONF_CH1_SZ_256M;
-		break;
-	case SZ_512M:
-		ret = SG_MEMCONF_CH1_SZ_512M;
-		break;
-	case SZ_1G:
-		ret = SG_MEMCONF_CH1_SZ_1G;
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	switch (num) {
-	case 1:
-		ret |= SG_MEMCONF_CH1_NUM_1;
-		break;
-	case 2:
-		ret |= SG_MEMCONF_CH1_NUM_2;
-		break;
-	default:
-		BUG();
-		break;
-	}
-	return ret;
-}
-
-void memconf_init(void)
-{
-	u32 tmp;
-
-	/* Set DDR size */
-	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-	tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-	writel(tmp, SG_MEMCONF);
-}