ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

2 files changed, 37 insertions, 0 deletions

diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
new file mode 100644
index 0000000000..58af1add58
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= early-clk-ph1-ld4.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
new file mode 100644
index 0000000000..f646c9b7df
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+
+	tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+	if (spl_boot_device() != BOOT_DEVICE_NAND)
+		tmp &= ~SC_RSTCTRL_NRST_NAND;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+
+	return 0;
+}