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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:34 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 46abfcc99e04efa75ed293bd871092c31d0f3be3 (patch) | |
| tree | e8574e16ce94aadb203124a6c8a52a105a64c194 /arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | |
| parent | 8353266825d7b7d673519bce3a54cdddf2c3d459 (diff) | |
| download | talos-obmc-uboot-46abfcc99e04efa75ed293bd871092c31d0f3be3.tar.gz talos-obmc-uboot-46abfcc99e04efa75ed293bd871092c31d0f3be3.zip | |
ARM: uniphier: rework struct uniphier_board_data
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it. It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/umc-ph1-pro4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 261f7cfce7..16c82645c4 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -146,39 +146,39 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000103, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size); ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size); ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0); writel(0x00000103, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size); ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); - ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size, - bd->dram_ch0_width); + ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch[0].size, + bd->dram_ch[0].width); if (ret) return ret; - ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size, - bd->dram_ch1_width); + ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch[1].size, + bd->dram_ch[1].width); if (ret) return ret; |
