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authorThierry Reding <treding@nvidia.com>2015-08-20 11:42:19 +0200
committerTom Warren <twarren@nvidia.com>2015-09-16 16:10:22 -0700
commitc043c0259cd88f39cdca5f98af8b10f178660745 (patch)
tree6def8ed72abc3fb8155956a6dff7f9c24fae3952 /arch/arm/mach-tegra/tegra210
parent70bcb43e7d943f5f437e84594e0b890b0869be23 (diff)
downloadtalos-obmc-uboot-c043c0259cd88f39cdca5f98af8b10f178660745.tar.gz
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ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra210')
-rw-r--r--arch/arm/mach-tegra/tegra210/clock.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 830a33ffc9..146bb6453a 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -998,6 +998,17 @@ void clock_early_init(void)
udelay(2);
}
+unsigned int clk_m_get_rate(unsigned parent_rate)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 value, div;
+
+ value = readl(&clkrst->crc_spare_reg0);
+ div = ((value >> 2) & 0x3) + 1;
+
+ return parent_rate / div;
+}
+
void arch_timer_init(void)
{
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
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