diff options
| author | Marek Vasut <marex@denx.de> | 2015-08-24 11:51:46 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-09-04 11:54:20 +0200 |
| commit | 65d372c44c6fd7ba280c44704136c91a03618a27 (patch) | |
| tree | 3f0a5852eb26deb9a2da0808cb219d36a48c5bcc /arch/arm/mach-socfpga | |
| parent | 129adf5bf4769cd93f05e53e6aab724894c31036 (diff) | |
| download | talos-obmc-uboot-65d372c44c6fd7ba280c44704136c91a03618a27.tar.gz talos-obmc-uboot-65d372c44c6fd7ba280c44704136c91a03618a27.zip | |
arm: socfpga: Assure ISWGRP 0 and 1 are inited
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 1186358a71..b6beaa2f22 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,13 +7,16 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/reset_manager.h> #include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) @@ -97,6 +100,9 @@ void socfpga_bridges_reset(int enable) /* brdmodrst */ writel(0xffffffff, &reset_manager_base->brg_mod_reset); } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { /* FPGA not ready, do nothing. */ |
