diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-10-08 11:31:47 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-10-17 20:16:13 -0400 |
| commit | 8626cb8021d92603cb6a305fb686510a8d14d6bd (patch) | |
| tree | b9cf15c37ee746aaae4adfa5e511ca577b0a98a6 /arch/arm/mach-keystone/clock.c | |
| parent | b9f06b360df8bb0abae810c4f75c539119d42683 (diff) | |
| download | talos-obmc-uboot-8626cb8021d92603cb6a305fb686510a8d14d6bd.tar.gz talos-obmc-uboot-8626cb8021d92603cb6a305fb686510a8d14d6bd.zip | |
ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/clock.c')
| -rw-r--r-- | arch/arm/mach-keystone/clock.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index fc3eadb3f2..6cb646734a 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -33,6 +33,11 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, }; +inline void pll_pa_clk_sel(void) +{ + setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK); +} + static void wait_for_completion(const struct pll_init_data *data) { int i; @@ -180,9 +185,8 @@ void configure_secondary_pll(const struct pll_init_data *data) sdelay(21000); /* Select the Output of PASS PLL as input to PASS */ - if (data->pll == PASS_PLL) - setbits_le32(keystone_pll_regs[data->pll].reg1, - CFG_PLLCTL1_PAPLL_MASK); + if (data->pll == PASS_PLL && cpu_is_k2hk()) + pll_pa_clk_sel(); /* Select the Output of ARM PLL as input to ARM */ if (data->pll == TETRIS_PLL) |
