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authorStephen Warren <swarren@wwwdotorg.org>2015-03-24 20:07:34 -0600
committerMarek Vasut <marex@denx.de>2015-04-14 05:47:59 +0200
commit79340db7f1f676b8eb5911f4993ebedf27009c0b (patch)
tree5291da5ab850b244c6614660037f90df72cc6e38 /arch/arm/mach-bcm283x
parent927c1fa266ead17acb09e9397dbd33578f3ee267 (diff)
downloadtalos-obmc-uboot-79340db7f1f676b8eb5911f4993ebedf27009c0b.tar.gz
talos-obmc-uboot-79340db7f1f676b8eb5911f4993ebedf27009c0b.zip
ARM: bcm2835: implement phys_to_bus/bus_to_phys
The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally access DRAM via this same L2 cache (although they always bypass the L1 cache). Peripherals select whether to use or bypass the cache via the top two bits of the bus address. An IOMMU exists between the ARM CPU and the rest of the system. This controls whether the ARM CPU's accesses use or bypass the L1 and/or L2 cache. This IOMMU is configured/controlled exclusively by the VideoCore CPU. In order for DRAM accesses made by the ARM core to be coherent with accesses made by other DMA peripherals, we must program a bus address into those peripherals that causes the peripheral's accesses to use the same set of caches that the ARM core's accesses will use. On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of the L2 cache. This corresponds to addresses based at 0x40000000. On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of the L2 cache. This corresponds to addresses based at 0xc0000000. This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according to those rules. For full details of this setup, please see Dom Cobley's description at: http://lists.denx.de/pipermail/u-boot/2015-March/208201.html http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038 https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'arch/arm/mach-bcm283x')
-rw-r--r--arch/arm/mach-bcm283x/Kconfig3
-rw-r--r--arch/arm/mach-bcm283x/Makefile2
-rw-r--r--arch/arm/mach-bcm283x/phys2bus.c22
3 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index b43f2d91fd..0c04c301b2 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -23,6 +23,9 @@ config DM_SERIAL
config DM_GPIO
default y
+config PHYS_TO_BUS
+ default y
+
config SYS_BOARD
default "rpi" if TARGET_RPI
default "rpi_2" if TARGET_RPI_2
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index 2505428bab..ac27d00e2a 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -5,4 +5,4 @@
#
obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o
-obj-y += init.o reset.o timer.o mbox.o
+obj-y += init.o reset.o timer.o mbox.o phys2bus.o
diff --git a/arch/arm/mach-bcm283x/phys2bus.c b/arch/arm/mach-bcm283x/phys2bus.c
new file mode 100644
index 0000000000..fc1c29905d
--- /dev/null
+++ b/arch/arm/mach-bcm283x/phys2bus.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2015 Stephen Warren
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <phys2bus.h>
+
+unsigned long phys_to_bus(unsigned long phys)
+{
+#ifdef CONFIG_BCM2836
+ return 0xc0000000 | phys;
+#else
+ return 0x40000000 | phys;
+#endif
+}
+
+unsigned long bus_to_phys(unsigned long bus)
+{
+ return bus & ~0xc0000000;
+}
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