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| author | Bo Shen <voice.shen@atmel.com> | 2015-03-27 14:23:33 +0800 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-04-01 01:04:29 +0200 |
| commit | 72cb3b6b54e99959f84456e448aa3db9f776f8a5 (patch) | |
| tree | 0c5951ef1b5a4ad9ff4b48957472812324e45aff /arch/arm/mach-at91 | |
| parent | 23ac62d4c72c9be762cb8613b8269599295f7c88 (diff) | |
| download | talos-obmc-uboot-72cb3b6b54e99959f84456e448aa3db9f776f8a5.tar.gz talos-obmc-uboot-72cb3b6b54e99959f84456e448aa3db9f776f8a5.zip | |
ARM: atmel: arm926ejs: fix clock configuration
Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.
Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/mach-at91')
| -rw-r--r-- | arch/arm/mach-at91/arm926ejs/clock.c | 54 |
1 files changed, 28 insertions, 26 deletions
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index f363982d03..8d6934e324 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock) void at91_plla_init(u32 pllar) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) + ; } void at91_pllb_init(u32 pllbr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllbr, &pmc->pllbr); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) + ; } void at91_mck_init(u32 mckr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; u32 tmp; tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); + tmp &= ~AT91_PMC_MCKR_PRES_MASK; + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK; writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { - timeout--; - if (timeout == 0) - break; - } + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_MDIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_CSS_MASK; + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; } void at91_periph_clk_enable(int id) |
