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authorWenyou Yang <wenyou.yang@atmel.com>2015-11-05 16:37:50 +0800
committerAndreas Bießmann <andreas.devel@googlemail.com>2015-11-30 22:27:54 +0100
commit5906d2aa0cb461fc10c9d429d9b38a6b1265afe2 (patch)
tree5059b48b60dc7869941cf30b78ae73646dfa1890 /arch/arm/mach-at91
parent5cb9dfa031c01ed747a11b18bdf64ba598a3597f (diff)
downloadtalos-obmc-uboot-5906d2aa0cb461fc10c9d429d9b38a6b1265afe2.tar.gz
talos-obmc-uboot-5906d2aa0cb461fc10c9d429d9b38a6b1265afe2.zip
arm: at91/spl: matrix: remove matrix write protection code
On processor reset, the matrix write protection is disabled, so no need to disable/enable write protection when writing the matrix registers. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/matrix.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
index cf363861c6..452a6b995c 100644
--- a/arch/arm/mach-at91/matrix.c
+++ b/arch/arm/mach-at91/matrix.c
@@ -15,10 +15,6 @@ void matrix_init(void)
struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
int i;
- /* Disable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
for (i = 4; i <= 10; i++) {
writel(0x000f0f0f, &h64mx->ssr[i]);
@@ -44,8 +40,4 @@ void matrix_init(void)
/* Configure Programmable Security peripherals on matrix 32 */
writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);
-
- /* Enable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
}
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