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| author | Wenyou Yang <wenyou.yang@atmel.com> | 2015-09-22 14:59:25 +0800 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-11-03 14:21:30 +0100 |
| commit | 79667b7b769405ec510baf2afed566eae58ec713 (patch) | |
| tree | e28a44fc5b06321e1007254de3eee7f0fa6ee7ab /arch/arm/mach-at91/armv7/clock.c | |
| parent | ce39680f7e560236213487ac6bf1baa66b6f74e3 (diff) | |
| download | talos-obmc-uboot-79667b7b769405ec510baf2afed566eae58ec713.tar.gz talos-obmc-uboot-79667b7b769405ec510baf2afed566eae58ec713.zip | |
mmc: sdhci: Fix the SD clock stop sequence
According to the SDHC specification, stopping the SD Clock is by setting
the SD Clock Enable bit in the Clock Control register at 0, instead of
setting all bits at 0.
Before stopping the SD clock, we need to make sure all SD transactions
to complete, so add checking the CMD and DAT bits in the Presen State
register, before stopping the SD clock.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/armv7/clock.c')
0 files changed, 0 insertions, 0 deletions
