Merge branch 'master' of git://git.denx.de/u-boot-sunxi

12 files changed, 270 insertions, 38 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 8a803851e4..04c6d58186 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -31,7 +31,7 @@ struct sunxi_ccm_reg {
 	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
 	u32 pll9_cfg;		/* 0x44 pll9 control */
 	u32 pll10_cfg;		/* 0x48 pll10 control */
-	u32 reserved8;
+	u32 pll11_cfg;		/* 0x4c pll11 (ddr1) control (A33 only) */
 	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
 	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
 	u32 apb2_div;		/* 0x58 APB2 divide ratio */
@@ -63,7 +63,8 @@ struct sunxi_ccm_reg {
 	u32 reserved12[7];
 	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
 	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
-	u32 reserved13[2];
+	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
+	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
@@ -126,7 +127,9 @@ struct sunxi_ccm_reg {
 	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
 	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
 	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
-	u32 reserved22[5];
+	u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
+	u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
+	u32 reserved22[3];
 	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
 	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
 	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
@@ -195,6 +198,11 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_K_SHIFT		4
 #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
 
+#define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
+#define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
+#define CCM_PLL11_CTRL_UPD		(0x1 << 30)
+#define CCM_PLL11_CTRL_EN		(0x1 << 31)
+
 #define AHB1_ABP1_DIV_DEFAULT		0x00002020
 
 #define AXI_GATE_OFFSET_DRAM		0
@@ -216,6 +224,7 @@ struct sunxi_ccm_reg {
 
 /* ahb_gate1 offsets */
 #define AHB_GATE_OFFSET_DRC0		25
+#define AHB_GATE_OFFSET_DE_FE0		14
 #define AHB_GATE_OFFSET_DE_BE0		12
 #define AHB_GATE_OFFSET_HDMI		11
 #define AHB_GATE_OFFSET_LCD1		5
@@ -248,12 +257,23 @@ struct sunxi_ccm_reg {
 
 #define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
 
+#define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK	(0xf << 0)
 #define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
 #define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
 #define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
 #define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
 
+#define CCM_DRAMPLL_CFG_SRC_PLL5	(0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11	(0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK	(0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET		(0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	25
 #define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
 
 #define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
 #define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
@@ -285,8 +305,10 @@ struct sunxi_ccm_reg {
 #else
 #define MBUS_CLK_DEFAULT		0x81000003 /* PLL6 / 4 */
 #endif
+#define MBUS_CLK_GATE			(0x1 << 31)
 
 #define CCM_PLL5_PATTERN		0xd1303333
+#define CCM_PLL11_PATTERN		0xf5860000
 
 /* ahb_reset0 offsets */
 #define AHB_RESET_OFFSET_GMAC		17
@@ -299,7 +321,9 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_SS		5
 
 /* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT		26
 #define AHB_RESET_OFFSET_DRC0		25
+#define AHB_RESET_OFFSET_DE_FE0		14
 #define AHB_RESET_OFFSET_DE_BE0		12
 #define AHB_RESET_OFFSET_HDMI		11
 #define AHB_RESET_OFFSET_LCD1		5
@@ -326,6 +350,7 @@ struct sunxi_ccm_reg {
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
 unsigned int clock_get_pll6(void);
 #endif
 
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f403742d3a..63b161ab03 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -37,7 +37,7 @@
 #define SUNXI_MMC1_BASE			0x01c10000
 #define SUNXI_MMC2_BASE			0x01c11000
 #define SUNXI_MMC3_BASE			0x01c12000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
 #define SUNXI_USB0_BASE			0x01c13000
 #define SUNXI_USB1_BASE			0x01c14000
 #endif
@@ -45,12 +45,13 @@
 #define SUNXI_HDMI_BASE			0x01c16000
 #define SUNXI_SPI2_BASE			0x01c17000
 #define SUNXI_SATA_BASE			0x01c18000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
 #define SUNXI_PATA_BASE			0x01c19000
 #define SUNXI_ACE_BASE			0x01c1a000
 #define SUNXI_TVE1_BASE			0x01c1b000
 #define SUNXI_USB2_BASE			0x01c1c000
-#else
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
 #define SUNXI_USB0_BASE			0x01c19000
 #define SUNXI_USB1_BASE			0x01c1a000
 #define SUNXI_USB2_BASE			0x01c1b000
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index aedd1941d5..273f80fe88 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -18,8 +18,10 @@
 /* dram regs definition */
 #if defined(CONFIG_MACH_SUN6I)
 #include <asm/arch/dram_sun6i.h>
-#elif defined(CONFIG_MACH_SUN8I)
-#include <asm/arch/dram_sun8i.h>
+#elif defined(CONFIG_MACH_SUN8I_A23)
+#include <asm/arch/dram_sun8i_a23.h>
+#elif defined(CONFIG_MACH_SUN8I_A33)
+#include <asm/arch/dram_sun8i_a33.h>
 #else
 #include <asm/arch/dram_sun4i.h>
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h
index 06adee2723..06adee2723 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
new file mode 100644
index 0000000000..afe6dc8eba
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
@@ -0,0 +1,179 @@
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_A33_H
+#define _SUNXI_DRAM_SUN8I_A33_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u8 res0[0x4];		/* 0x0c */
+	u32 mcr0_0;		/* 0x10 */
+	u32 mcr1_0;		/* 0x14 */
+	u32 mcr0_1;		/* 0x18 */
+	u32 mcr1_1;		/* 0x1c */
+	u32 mcr0_2;		/* 0x20 */
+	u32 mcr1_2;		/* 0x24 */
+	u32 mcr0_3;		/* 0x28 */
+	u32 mcr1_3;		/* 0x2c */
+	u32 mcr0_4;		/* 0x30 */
+	u32 mcr1_4;		/* 0x34 */
+	u32 mcr0_5;		/* 0x38 */
+	u32 mcr1_5;		/* 0x3c */
+	u32 mcr0_6;		/* 0x40 */
+	u32 mcr1_6;		/* 0x44 */
+	u32 mcr0_7;		/* 0x48 */
+	u32 mcr1_7;		/* 0x4c */
+	u32 mcr0_8;		/* 0x50 */
+	u32 mcr1_8;		/* 0x54 */
+	u32 mcr0_9;		/* 0x58 */
+	u32 mcr1_9;		/* 0x5c */
+	u32 mcr0_10;		/* 0x60 */
+	u32 mcr1_10;		/* 0x64 */
+	u32 mcr0_11;		/* 0x68 */
+	u32 mcr1_11;		/* 0x6c */
+	u32 mcr0_12;		/* 0x70 */
+	u32 mcr1_12;		/* 0x74 */
+	u32 mcr0_13;		/* 0x78 */
+	u32 mcr1_13;		/* 0x7c */
+	u32 mcr0_14;		/* 0x80 */
+	u32 mcr1_14;		/* 0x84 */
+	u32 mcr0_15;		/* 0x88 */
+	u32 mcr1_15;		/* 0x8c */
+	u32 bwcr;		/* 0x90 */
+	u32 maer;		/* 0x94 */
+	u32 mapr;		/* 0x98 */
+	u32 mcgcr;		/* 0x9c */
+	u32 bwctr;		/* 0xa0 */
+	u8 res2[0x8];		/* 0xa4 */
+	u32 swoffr;		/* 0xac */
+	u8 res3[0x10];		/* 0xb0 */
+	u32 swonr;		/* 0xc0 */
+	u8 res4[0x3c];		/* 0xc4 */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u32 pir;		/* 0x00 */
+	u32 pwrctl;		/* 0x04 */
+	u32 mrctrl0;		/* 0x08 */
+	u32 clken;		/* 0x0c */
+	u32 pgsr0;		/* 0x10 */
+	u32 pgsr1;		/* 0x14 */
+	u32 statr;		/* 0x18 */
+	u8 res1[0x14];		/* 0x1c */
+	u32 mr0;		/* 0x30 */
+	u32 mr1;		/* 0x34 */
+	u32 mr2;		/* 0x38 */
+	u32 mr3;		/* 0x3c */
+	u32 pllgcr;		/* 0x40 */
+	u32 ptr0;		/* 0x44 */
+	u32 ptr1;		/* 0x48 */
+	u32 ptr2;		/* 0x4c */
+	u32 ptr3;		/* 0x50 */
+	u32 ptr4;		/* 0x54 */
+	u32 dramtmg0;		/* 0x58 dram timing parameters register 0 */
+	u32 dramtmg1;		/* 0x5c dram timing parameters register 1 */
+	u32 dramtmg2;		/* 0x60 dram timing parameters register 2 */
+	u32 dramtmg3;		/* 0x64 dram timing parameters register 3 */
+	u32 dramtmg4;		/* 0x68 dram timing parameters register 4 */
+	u32 dramtmg5;		/* 0x6c dram timing parameters register 5 */
+	u32 dramtmg6;		/* 0x70 dram timing parameters register 6 */
+	u32 dramtmg7;		/* 0x74 dram timing parameters register 7 */
+	u32 dramtmg8;		/* 0x78 dram timing parameters register 8 */
+	u32 odtcfg;		/* 0x7c */
+	u32 pitmg0;		/* 0x80 */
+	u32 pitmg1;		/* 0x84 */
+	u8 res2[0x4];		/* 0x88 */
+	u32 rfshctl0;		/* 0x8c */
+	u32 rfshtmg;		/* 0x90 */
+	u32 rfshctl1;		/* 0x94 */
+	u32 pwrtmg;		/* 0x98 */
+	u8  res3[0x20];		/* 0x9c */
+	u32 dqsgmr;		/* 0xbc */
+	u32 dtcr;		/* 0xc0 */
+	u32 dtar0;		/* 0xc4 */
+	u32 dtar1;		/* 0xc8 */
+	u32 dtar2;		/* 0xcc */
+	u32 dtar3;		/* 0xd0 */
+	u32 dtdr0;		/* 0xd4 */
+	u32 dtdr1;		/* 0xd8 */
+	u32 dtmr0;		/* 0xdc */
+	u32 dtmr1;		/* 0xe0 */
+	u32 dtbmr;		/* 0xe4 */
+	u32 catr0;		/* 0xe8 */
+	u32 catr1;		/* 0xec */
+	u32 dtedr0;		/* 0xf0 */
+	u32 dtedr1;		/* 0xf4 */
+	u8 res4[0x8];		/* 0xf8 */
+	u32 pgcr0;		/* 0x100 */
+	u32 pgcr1;		/* 0x104 */
+	u32 pgcr2;		/* 0x108 */
+	u8 res5[0x4];		/* 0x10c */
+	u32 iovcr0;		/* 0x110 */
+	u32 iovcr1;		/* 0x114 */
+	u32 dqsdr;		/* 0x118 */
+	u32 dxccr;		/* 0x11c */
+	u32 odtmap;		/* 0x120 */
+	u32 zqctl0;		/* 0x124 */
+	u32 zqctl1;		/* 0x128 */
+	u8 res6[0x14];		/* 0x12c */
+	u32 zqcr0;		/* 0x140 zq control register 0 */
+	u32 zqcr1;		/* 0x144 zq control register 1 */
+	u32 zqcr2;		/* 0x148 zq control register 2 */
+	u32 zqsr0;		/* 0x14c zq status register 0 */
+	u32 zqsr1;		/* 0x150 zq status register 1 */
+	u8 res7[0x6c];		/* 0x154 */
+	u32 sched;		/* 0x1c0 */
+	u32 perfhpr0;		/* 0x1c4 */
+	u32 perfhpr1;		/* 0x1c8 */
+	u32 perflpr0;		/* 0x1cc */
+	u32 perflpr1;		/* 0x1d0 */
+	u32 perfwr0;		/* 0x1d4 */
+	u32 perfwr1;		/* 0x1d8 */
+};
+
+#define DXnGTR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
+#define DXnGCR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
+#define DXnGSR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
+#define DXnGSR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
+#define DXnGSR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(7 << 12)
+#define MCTL_CR_BUSW8			(0 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			(0x4 << 20)
+#define MCTL_CR_CS1_CONTROL(x)		((x) << 24)
+
+/* DRAM control (sunxi_mctl_ctl_reg) register constants */
+#define MCTL_MR0			0x1c70 /* CL=11, WR=12 */
+#define MCTL_MR1			0x40
+#define MCTL_MR2			0x18 /* CWL=8 */
+#define MCTL_MR3			0x0
+
+#endif /* _SUNXI_DRAM_SUN8I_A33_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index ae7cbb7e78..59d8210e88 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -203,8 +203,10 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_PULL_DOWN	2
 
 /* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_VBUS_DETECT	8
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE	9
+#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
 
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
@@ -216,4 +218,10 @@ int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+int axp_gpio_init(void);
+#else
+static inline int axp_gpio_init(void) { return 0; }
+#endif
+
 #endif /* _SUNXI_GPIO_H */
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 74833b51d1..cb52e64873 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,8 +43,7 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
-    defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
 	u32 res2[64];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
new file mode 100644
index 0000000000..9c4372a881
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Sunxi PMIC bus access helpers header
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_PMIC_BUS_H
+#define _SUNXI_PMIS_BUS_H
+
+int pmic_bus_init(void);
+int pmic_bus_read(u8 reg, u8 *data);
+int pmic_bus_write(u8 reg, u8 data);
+int pmic_bus_setbits(u8 reg, u8 bits);
+int pmic_bus_clrbits(u8 reg, u8 bits);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index 60a5bd8c85..9df3744521 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -23,4 +23,7 @@ void sdelay(unsigned long);
  */
 void return_to_fel(uint32_t lr, uint32_t sp);
 
+/* Board / SoC level designware gmac init */
+int sunxi_gmac_initialize(bd_t *bis);
+
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 9a5e488a38..a665309803 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
 	struct sunxi_timer timer[6];	/* We have 6 timers */
 	u8 res2[16];
 	struct sunxi_avs avs;
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
 	struct sunxi_wdog wdog;	/* 0x90 */
 	/* XXX the following is not accurate for sun5i/sun7i */
 	struct sunxi_64cnt cnt64;	/* 0xa0 */
@@ -77,7 +77,8 @@ struct sunxi_timer_reg {
 	struct sunxi_tgp tgp[4];
 	u8 res5[8];
 	u32 cpu_cfg;
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
 	u8 res3[16];
 	struct sunxi_wdog wdog[5];	/* We have 5 watchdogs */
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h
new file mode 100644
index 0000000000..b7b831e24a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h
@@ -0,0 +1,20 @@
+/*
+ * Sunxi usb-phy code
+ *
+ * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+int sunxi_usb_phy_probe(void);
+int sunxi_usb_phy_remove(void);
+void sunxi_usb_phy_init(int index);
+void sunxi_usb_phy_exit(int index);
+void sunxi_usb_phy_power_on(int index);
+void sunxi_usb_phy_power_off(int index);
+int sunxi_usb_phy_vbus_detect(int index);
+void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
deleted file mode 100644
index ab0f272e41..0000000000
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Sunxi usb-controller code shared between the ehci and musb controllers
- *
- * Copyright (C) 2014 Roman Byshko
- *
- * Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern const struct musb_platform_ops sunxi_musb_ops;
-
-void *sunxi_usbc_get_io_base(int index);
-int sunxi_usbc_request_resources(int index);
-int sunxi_usbc_free_resources(int index);
-void sunxi_usbc_enable(int index);
-void sunxi_usbc_disable(int index);
-void sunxi_usbc_vbus_enable(int index);
-void sunxi_usbc_vbus_disable(int index);
-int sunxi_usbc_vbus_detect(int index);
-void sunxi_usbc_enable_squelch_detect(int index, int enable);