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| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:34 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:23 +0200 |
| commit | 5f14d9197edc5476d3453349651d295df2dcb8c3 (patch) | |
| tree | 63ab040dfd7d3e8b89f29db11e3876c681befcd1 /arch/arm/include | |
| parent | dc7a9e64bfdd0504e1a985b6a6121ed1b5a015d7 (diff) | |
| download | talos-obmc-uboot-5f14d9197edc5476d3453349651d295df2dcb8c3.tar.gz talos-obmc-uboot-5f14d9197edc5476d3453349651d295df2dcb8c3.zip | |
OMAP5: clocks: Change clock settings as required for ES1.0 silicon.
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clocks.h | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 55145bbee2..cf6022da2f 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -473,9 +473,11 @@ struct omap5_prcm_regs { u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ u32 pad214; /* 4ae07884 */ u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ - u32 pad215[197]; /* 4ae0788c */ + u32 pad215[1]; /* 4ae0788c */ + u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */ + u32 pad216[195]; u32 prm_vc_val_bypass; /* 4ae07ba0 */ - u32 pad216[4]; + u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ }; @@ -514,6 +516,10 @@ struct omap5_prcm_regs { /* CM_IDLEST_DPLL fields */ #define ST_DPLL_CLK_MASK 1 +/* SGX */ +#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) +#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + /* CM_CLKSEL_DPLL */ #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) @@ -591,6 +597,7 @@ struct omap5_prcm_regs { /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) /* CM_WKUP_GPTIMER1_CLKCTRL */ #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) @@ -610,6 +617,12 @@ struct omap5_prcm_regs { #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) +/* CM_WKUPAON_SCRM_CLKCTRL */ +#define OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) +#define OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 @@ -663,7 +676,7 @@ struct dpll_regs { u32 cm_div_h12_dpll; u32 cm_div_h13_dpll; u32 cm_div_h14_dpll; - u32 reserved[2]; + u32 reserved[3]; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll; }; |
