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| author | Alison Wang <b18965@freescale.com> | 2015-08-18 11:22:05 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-09-01 21:49:27 -0500 |
| commit | 997992201541dcec67cf1ed568e442efd57cbac4 (patch) | |
| tree | 3568e60f1361e4461273893e2c87a4ab7e8ef684 /arch/arm/include/asm | |
| parent | 03c22449c5b7daff0a43291b34564a52660b83b8 (diff) | |
| download | talos-obmc-uboot-997992201541dcec67cf1ed568e442efd57cbac4.tar.gz talos-obmc-uboot-997992201541dcec67cf1ed568e442efd57cbac4.zip | |
armv8: fsl-lsch3: Rewrite MMU translation table entries
This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 8 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 1ea240ef49..96d6c98cb8 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -19,6 +19,7 @@ #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 04fa0be64c..0c928d40e7 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,6 +65,7 @@ /* * Section */ +#define PMD_SECT_NON_SHARE (0 << 8) #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) #define PMD_SECT_AF (1 << 10) @@ -110,8 +111,13 @@ TCR_T0SZ(VA_BITS)) #ifndef __ASSEMBLY__ + void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); + u64 section, u64 memory_type, + u64 share); +void set_pgtable_table(u64 *page_table, u64 index, + u64 *table_addr); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); |
