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| author | Fabio Estevam <festevam@gmail.com> | 2012-04-30 08:12:02 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:32 +0200 |
| commit | 70cc86a6307ab4de4a2cd1125e5b9c857242a4e3 (patch) | |
| tree | 4d4a3284fe39dce0a28d3a5042ad9208f8678ea0 /arch/arm/include/asm | |
| parent | 6a376046ef3b2417cf9fbfbfad300fa6f026c816 (diff) | |
| download | talos-obmc-uboot-70cc86a6307ab4de4a2cd1125e5b9c857242a4e3.tar.gz talos-obmc-uboot-70cc86a6307ab4de4a2cd1125e5b9c857242a4e3.zip | |
mx5: Add clock config interface
mx5: Add clock config interface
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/clock.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/crm_regs.h | 6 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index e822809d7f..35ee8155de 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -33,6 +33,9 @@ enum mxc_clock { MXC_CSPI_CLK, MXC_FEC_CLK, MXC_SATA_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, }; unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); @@ -40,7 +43,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); - +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); void set_usb_phy2_clk(void); void enable_usb_phy2_clk(unsigned char enable); void set_usboh3_clk(void); diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index bdeafbc0df..4e0fc1bc1d 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -76,6 +76,9 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif u32 cmeor; }; @@ -84,6 +87,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 /* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 |
