Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Conflicts:
	spl/Makefile

4 files changed, 53 insertions, 40 deletions

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f76e4897e9..36b98c83e1 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -38,6 +38,7 @@
 #define EXYNOS4_CLOCK_BASE		0x10030000
 #define EXYNOS4_SYSTIMER_BASE		0x10050000
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
+#define EXYNOS4_TZPC_BASE		0x10110000
 #define EXYNOS4_MIU_BASE		0x10600000
 #define EXYNOS4_DMC0_BASE		0x10400000
 #define EXYNOS4_DMC1_BASE		0x10410000
@@ -74,6 +75,7 @@
 #define EXYNOS4X12_CLOCK_BASE		0x10030000
 #define EXYNOS4X12_SYSTIMER_BASE	0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE	0x10060000
+#define EXYNOS4X12_TZPC_BASE		0x10110000
 #define EXYNOS4X12_DMC0_BASE		0x10600000
 #define EXYNOS4X12_DMC1_BASE		0x10610000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
@@ -107,6 +109,7 @@
 #define EXYNOS5_POWER_BASE		0x10040000
 #define EXYNOS5_SWRESET			0x10040400
 #define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 #define EXYNOS5_DMC_PHY0_BASE		0x10C00000
@@ -233,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b725..3b147b86e3 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-	return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h
index 7e0158efb6..cad35694f6 100644
--- a/arch/arm/include/asm/arch-exynos/tmu.h
+++ b/arch/arm/include/asm/arch-exynos/tmu.h
@@ -21,38 +21,30 @@
 #define __ASM_ARCH_TMU_H
 
 struct exynos5_tmu_reg {
-	unsigned triminfo;
-	unsigned rsvd1;
-	unsigned rsvd2;
-	unsigned rsvd3;
-	unsigned rsvd4;
-	unsigned triminfo_control;
-	unsigned rsvd5;
-	unsigned rsvd6;
-	unsigned tmu_control;
-	unsigned rsvd7;
-	unsigned tmu_status;
-	unsigned sampling_internal;
-	unsigned counter_value0;
-	unsigned counter_value1;
-	unsigned rsvd8;
-	unsigned rsvd9;
-	unsigned current_temp;
-	unsigned rsvd10;
-	unsigned rsvd11;
-	unsigned rsvd12;
-	unsigned threshold_temp_rise;
-	unsigned threshold_temp_fall;
-	unsigned rsvd13;
-	unsigned rsvd14;
-	unsigned past_temp3_0;
-	unsigned past_temp7_4;
-	unsigned past_temp11_8;
-	unsigned past_temp15_12;
-	unsigned inten;
-	unsigned intstat;
-	unsigned intclear;
-	unsigned rsvd15;
-	unsigned emul_con;
+	u32 triminfo;
+	u32 rsvd1[4];
+	u32 triminfo_control;
+	u32 rsvd5[2];
+	u32 tmu_control;
+	u32 rsvd7;
+	u32 tmu_status;
+	u32 sampling_internal;
+	u32 counter_value0;
+	u32 counter_value1;
+	u32 rsvd8[2];
+	u32 current_temp;
+	u32 rsvd10[3];
+	u32 threshold_temp_rise;
+	u32 threshold_temp_fall;
+	u32 rsvd13[2];
+	u32 past_temp3_0;
+	u32 past_temp7_4;
+	u32 past_temp11_8;
+	u32 past_temp15_12;
+	u32 inten;
+	u32 intstat;
+	u32 intclear;
+	u32 rsvd15;
+	u32 emul_con;
 };
 #endif /* __ASM_ARCH_TMU_H */
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h
index c5eb4b1cc2..4d9c3a32fb 100644
--- a/arch/arm/include/asm/arch-exynos/tzpc.h
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -47,6 +47,26 @@ struct exynos_tzpc {
 	unsigned int pcellid2;
 	unsigned int pcellid3;
 };
+
+#define EXYNOS4_NR_TZPC_BANKS		6
+#define EXYNOS5_NR_TZPC_BANKS		10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET		0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+void tzpc_init(void);
+
 #endif
 
 #endif