diff options
| author | Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> | 2015-06-01 18:37:16 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-06-08 08:41:54 +0200 |
| commit | d348a943e77ed72dd809cecf03365552545382b2 (patch) | |
| tree | bae29b560def8ca251f63b3ef9b914af830b0a4f /arch/arm/include/asm/arch-vf610 | |
| parent | ae89bb0d363eba33074106309c81c02f84b91ef8 (diff) | |
| download | talos-obmc-uboot-d348a943e77ed72dd809cecf03365552545382b2.tar.gz talos-obmc-uboot-d348a943e77ed72dd809cecf03365552545382b2.zip | |
dm: gpio: vf610: Add GPIO driver support
Add GPIO driver support to Freescale VF610
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/gpio.h | 29 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 5 |
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h new file mode 100644 index 0000000000..622b8f0dea --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { + unsigned int chip; + u32 base; + const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 202198133c..7df3b1e392 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -81,6 +81,11 @@ #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) /* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) |
