diff options
| author | Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> | 2015-06-01 18:37:19 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-06-08 08:41:55 +0200 |
| commit | 098d85840ebd72c87a547a87df2654a3ff7da725 (patch) | |
| tree | bfb4210a7aba413287185f4c3cb9baed32f6260d /arch/arm/include/asm/arch-vf610 | |
| parent | 30748d81d0b33f04c86b5b96aab2e8bf8d330ea2 (diff) | |
| download | talos-obmc-uboot-098d85840ebd72c87a547a87df2654a3ff7da725.tar.gz talos-obmc-uboot-098d85840ebd72c87a547a87df2654a3ff7da725.zip | |
arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adadd79..e5a5c6d28f 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, }; void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a5a5..fdb45e9954 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,8 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -206,6 +208,8 @@ struct anadig_reg { #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) |
