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author | Mathieu J. Poirier <mathieu.poirier@linaro.org> | 2012-07-31 08:59:27 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:20 +0200 |
commit | 101a769d75ffd06b7316d7bd4e896b95af7cb6d4 (patch) | |
tree | 59140ce1918b2830c5430a8bd5dd452b9c70c63e /arch/arm/include/asm/arch-u8500/prcmu.h | |
parent | 81637e26b38ff532f20663abb897be0ea0931280 (diff) | |
download | talos-obmc-uboot-101a769d75ffd06b7316d7bd4e896b95af7cb6d4.tar.gz talos-obmc-uboot-101a769d75ffd06b7316d7bd4e896b95af7cb6d4.zip |
snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch/arm/include/asm/arch-u8500/prcmu.h')
-rw-r--r-- | arch/arm/include/asm/arch-u8500/prcmu.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 1fd4d2a564..9862eb3dd9 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -28,6 +28,7 @@ #define I2CWRITE 0 #define PRCMU_BASE U8500_PRCMU_BASE +#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE #define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) #define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) #define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) @@ -38,12 +39,15 @@ #define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) #define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) #define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) +#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC) +#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) #define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494) #define PRCM_TCR (PRCMU_BASE + 0x1C8) -#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) -#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) -#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) +#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) |