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| author | Tom Warren <twarren@nvidia.com> | 2015-02-02 13:22:29 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-07-28 10:30:19 -0700 |
| commit | 6c43f6c8d920caa1db01f5d0571a4d9ba720be15 (patch) | |
| tree | aa3cabc8a3354f298c2f0ec125094402d653fee3 /arch/arm/include/asm/arch-tegra210/tegra.h | |
| parent | 56079eccd18a65bd5eea2f6a665862932c61963c (diff) | |
| download | talos-obmc-uboot-6c43f6c8d920caa1db01f5d0571a4d9ba720be15.tar.gz talos-obmc-uboot-6c43f6c8d920caa1db01f5d0571a4d9ba720be15.zip | |
ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra210/tegra.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra210/tegra.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h new file mode 100644 index 0000000000..95c67fbb8e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/tegra.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_TEGRA_H_ +#define _TEGRA210_TEGRA_H_ + +#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include <asm/arch-tegra/tegra.h> + +#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA210_TEGRA_H_ */ |
