diff options
| author | Stefan Agner <stefan@agner.ch> | 2014-03-02 19:46:49 +0100 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:06 -0700 |
| commit | b1d615f3f10294c016cc424ef05e938f49af8117 (patch) | |
| tree | 09ebc45c451b358b127a37cc02a29469cdb07711 /arch/arm/include/asm/arch-tegra20 | |
| parent | b03f4b3742a728c13a89f3fbf8a9a2ec43061025 (diff) | |
| download | talos-obmc-uboot-b1d615f3f10294c016cc424ef05e938f49af8117.tar.gz talos-obmc-uboot-b1d615f3f10294c016cc424ef05e938f49af8117.zip | |
usb: tegra: fix PHY configuration
On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.
Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra20')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/usb.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h index 3d94cc73b8..bcd6570610 100644 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ b/arch/arm/include/asm/arch-tegra20/usb.h @@ -147,9 +147,14 @@ struct usb_ctlr { #define ULPI_DIR_TRIMMER_LOAD (1 << 24) #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) +/* PORTSC1, USB1 */ +#define PTS1_SHIFT 31 +#define PTS1_MASK (1 << PTS1_SHIFT) +#define STS1 (1 << 30) + /* PORTSC, USB2, USB3 */ #define PTS_SHIFT 30 #define PTS_MASK (3U << PTS_SHIFT) - #define STS (1 << 29) + #endif /* _TEGRA20_USB_H_ */ |
