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authorBryan Brinsko <bryan.brinsko@rockwellcollins.com>2015-03-24 11:25:12 -0500
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2015-04-16 14:59:33 +0200
commit97840b5d1fe0960134c3553a9d9d1c1cd1be784d (patch)
tree3ae40c9ca7eceb5306544d318e38e6dad6dcedb2 /arch/arm/include/asm/arch-socfpga/system_manager.h
parent9ba379ade789e41cc4132d622315f3f021a47b9b (diff)
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ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
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