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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-05-30 03:19:38 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-10 08:43:10 -0400 |
| commit | 97405d843ece2a53e67b801e02ee42005d26e172 (patch) | |
| tree | 13c4b866c44ebbbb7033f7490921fcb6dffa6004 /arch/arm/include/asm/arch-omap5 | |
| parent | 7f36c88f64ee1affd4db78b2c2f4a616abceb84c (diff) | |
| download | talos-obmc-uboot-97405d843ece2a53e67b801e02ee42005d26e172.tar.gz talos-obmc-uboot-97405d843ece2a53e67b801e02ee42005d26e172.zip | |
ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 86d4711a14..1affa4f666 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -81,7 +81,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22) /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 @@ -98,6 +98,12 @@ #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 +/* CM_CLKSEL_ABE_PLL_SYS */ +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 + /* CM_BYPCLK_DPLL_IVA */ #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 |
