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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-12 01:33:44 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:10 -0400
commit9100edecf8379c357037c34044757202f85480b2 (patch)
tree5bbadfcd754737a33219e857e46f34e73cb0563a /arch/arm/include/asm/arch-omap5/omap.h
parent47abc3df701d8bc26f311350aa523fc1d0f8ad4e (diff)
downloadtalos-obmc-uboot-9100edecf8379c357037c34044757202f85480b2.tar.gz
talos-obmc-uboot-9100edecf8379c357037c34044757202f85480b2.zip
ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/omap.h')
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 71935d8579..ba2775b0a3 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -168,6 +168,12 @@ struct s32ktimer {
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100
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