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| author | SRICHARAN R <r.sricharan@ti.com> | 2012-05-24 00:30:25 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:24 +0200 |
| commit | e423a8f76d8dac55d067fd4c0eea8f18fb8929dc (patch) | |
| tree | 6c5123c068efa1a67e1e13286dff8ff652ff97f5 /arch/arm/include/asm/arch-omap4 | |
| parent | 7fd5b9bfe4a66a0eec232ab36ddafdd823e263c2 (diff) | |
| download | talos-obmc-uboot-e423a8f76d8dac55d067fd4c0eea8f18fb8929dc.tar.gz talos-obmc-uboot-e423a8f76d8dac55d067fd4c0eea8f18fb8929dc.zip | |
ARM: OMAP4: Correct the lpddr2 io settings register value.
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap4')
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/omap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 47c5883025..03bd923145 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -112,7 +112,7 @@ #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C #define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 |
