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authorTom Rini <trini@konsulko.com>2016-02-21 07:56:16 -0500
committerTom Rini <trini@konsulko.com>2016-02-21 07:56:16 -0500
commit595af9db2422fa5ae734cfe615415b17a5098f34 (patch)
tree21a9287dd2998798c2dbb1613eefc7d5f5a58159 /arch/arm/include/asm/arch-mx6/imx-regs.h
parent03bfc78359a2d749252b7dfdbff33898f6da0385 (diff)
parent35c4ce5e20d3d10d1089ba336a248896faed284c (diff)
downloadtalos-obmc-uboot-595af9db2422fa5ae734cfe615415b17a5098f34.tar.gz
talos-obmc-uboot-595af9db2422fa5ae734cfe615415b17a5098f34.zip
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5c45bf6d6e..f3c26dc6e6 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -356,6 +356,30 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[32]; /* Master Domain Assignment */
+ u32 reserved3[96];
+ u32 pdap[104]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[88];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[55];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
/* WEIM registers */
struct weim {
u32 cs0gcr1;
@@ -414,6 +438,11 @@ struct src {
u32 gpr10;
};
+#define SRC_SCR_M4_ENABLE_OFFSET 22
+#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
+
/* GPR1 bitfields */
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
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