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authorWolfgang Denk <wd@denx.de>2011-11-16 20:24:51 +0100
committerWolfgang Denk <wd@denx.de>2011-11-16 20:24:51 +0100
commit0e62e0a72cba76205c93b6913b9ae267f8fe08dc (patch)
tree47ffbd76c315fbfc9024ed16927e0c58060d3af6 /arch/arm/include/asm/arch-mx28/regs-ocotp.h
parentf31f496e306489184c6963e0d56d0cf7b2c9cd0b (diff)
parent0c2dd9a05bdcf3b2b4880509ec690116873fe158 (diff)
downloadtalos-obmc-uboot-0e62e0a72cba76205c93b6913b9ae267f8fe08dc.tar.gz
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Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs are detected arm, davinci: da850/dm365 lowlevel cleanup omap5: Add omap5_evm board build support. omap4/5: Add support for booting with CH. omap5: emif: Add emif/ddr configurations required for omap5 evm omap5: clocks: Add clocks support for omap5 platform. omap5: Add minimal support for omap5430. omap: Checkpatch fixes omap4: make omap4 code common for future reuse GCC4.6: Squash warnings in onenand_base.c GCC4.6: Fix common/usb.c on xscale OneNAND: Add simple OneNAND SPL PXA: vpac270: Enable the new generic MMC driver PXA: Cleanup serial_pxa PXA: Drop csb226 and innokom boards (unmaintained) m28evk: Fix comment about the number of RAM banks mx31: Fix checkpatch warnings in generic.c mx31: Use proper IO accessor for GPR register mx31: Remove duplicate definition for GPR register qong: Use generic function for configuring GPR register M28EVK: Enable USB HOST support iMX28: Add USB HOST driver iMX28: Add USB and USB PHY register definitions M28: Add memory detection into SPL iMX28: Fix ARM vector handling M28: Add doc/README.m28 documentation M28: Add MMC SPL iMX28: Add support for DENX M28EVK board iMX28: Add u-boot.sb target to Makefile iMX28: Add image header generator tool iMX28: Add driver for internal RTC iMX28: Add GPMI NAND driver iMX28: Add APBH DMA driver iMX28: Add SPI driver iMX28: Add GPIO control iMX28: Add I2C bus driver iMX28: Add PINMUX control FEC: Add support for iMX28 quirks iMX28: Add SSP MMC driver iMX28: Initial support for iMX28 CPU MX25: zmx25: GCC4.6 fix build warnings da850: add new config file for AM18xx BeagleBoard: config: Switch to ttyO2 OMAP3: Change omap3_evm maintainer devkit8000: Fix NAND SPL on boards with 256MB NAND integrator: enable Vpp and disable flash protection integrator: add system controller header integrator: make flash writeable on boot integrator: use io-accessors for board init integrator: move text offset to config integrator: pass configs for core modules ARM: remove superfluous setting of arch_number in board specific code. SPL: Allow ARM926EJS to avoid compiling in the CPU support code integrator: do not test first part of the memory arm: a320: fix broken timer ARM: define CONFIG_MACH_TYPE for all ronetix boards dm646x: pass board revision info to kernel dm646x: add new configuration for dm6467T arm, davinci: Fix setting of the SDRAM configuration register arm, davinci: Remove the duplication of LPSC functions arm, davinci: Rename AM1808 lowlevel functions to DA850 da8xxevm: fix build error ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
Diffstat (limited to 'arch/arm/include/asm/arch-mx28/regs-ocotp.h')
-rw-r--r--arch/arm/include/asm/arch-mx28/regs-ocotp.h173
1 files changed, 173 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
new file mode 100644
index 0000000000..ea2fd7b167
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
@@ -0,0 +1,173 @@
+/*
+ * Freescale i.MX28 OCOTP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_OCOTP_H__
+#define __MX28_REGS_OCOTP_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_ocotp_regs {
+ mx28_reg(hw_ocotp_ctrl) /* 0x0 */
+ mx28_reg(hw_ocotp_data) /* 0x10 */
+ mx28_reg(hw_ocotp_cust0) /* 0x20 */
+ mx28_reg(hw_ocotp_cust1) /* 0x30 */
+ mx28_reg(hw_ocotp_cust2) /* 0x40 */
+ mx28_reg(hw_ocotp_cust3) /* 0x50 */
+ mx28_reg(hw_ocotp_crypto0) /* 0x60 */
+ mx28_reg(hw_ocotp_crypto1) /* 0x70 */
+ mx28_reg(hw_ocotp_crypto2) /* 0x80 */
+ mx28_reg(hw_ocotp_crypto3) /* 0x90 */
+ mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */
+ mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */
+ mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */
+ mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */
+ mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */
+ mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */
+ mx28_reg(hw_ocotp_swcap) /* 0x100 */
+ mx28_reg(hw_ocotp_custcap) /* 0x110 */
+ mx28_reg(hw_ocotp_lock) /* 0x120 */
+ mx28_reg(hw_ocotp_ops0) /* 0x130 */
+ mx28_reg(hw_ocotp_ops1) /* 0x140 */
+ mx28_reg(hw_ocotp_ops2) /* 0x150 */
+ mx28_reg(hw_ocotp_ops3) /* 0x160 */
+ mx28_reg(hw_ocotp_un0) /* 0x170 */
+ mx28_reg(hw_ocotp_un1) /* 0x180 */
+ mx28_reg(hw_ocotp_un2) /* 0x190 */
+ mx28_reg(hw_ocotp_rom0) /* 0x1a0 */
+ mx28_reg(hw_ocotp_rom1) /* 0x1b0 */
+ mx28_reg(hw_ocotp_rom2) /* 0x1c0 */
+ mx28_reg(hw_ocotp_rom3) /* 0x1d0 */
+ mx28_reg(hw_ocotp_rom4) /* 0x1e0 */
+ mx28_reg(hw_ocotp_rom5) /* 0x1f0 */
+ mx28_reg(hw_ocotp_rom6) /* 0x200 */
+ mx28_reg(hw_ocotp_rom7) /* 0x210 */
+ mx28_reg(hw_ocotp_srk0) /* 0x220 */
+ mx28_reg(hw_ocotp_srk1) /* 0x230 */
+ mx28_reg(hw_ocotp_srk2) /* 0x240 */
+ mx28_reg(hw_ocotp_srk3) /* 0x250 */
+ mx28_reg(hw_ocotp_srk4) /* 0x260 */
+ mx28_reg(hw_ocotp_srk5) /* 0x270 */
+ mx28_reg(hw_ocotp_srk6) /* 0x280 */
+ mx28_reg(hw_ocotp_srk7) /* 0x290 */
+ mx28_reg(hw_ocotp_version) /* 0x2a0 */
+};
+#endif
+
+#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16)
+#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16
+#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16)
+#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13)
+#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
+#define OCOTP_CTRL_ERROR (1 << 9)
+#define OCOTP_CTRL_BUSY (1 << 8)
+#define OCOTP_CTRL_ADDR_MASK 0x3f
+#define OCOTP_CTRL_ADDR_OFFSET 0
+
+#define OCOTP_DATA_DATA_MASK 0xffffffff
+#define OCOTP_DATA_DATA_OFFSET 0
+
+#define OCOTP_CUST_BITS_MASK 0xffffffff
+#define OCOTP_CUST_BITS_OFFSET 0
+
+#define OCOTP_CRYPTO_BITS_MASK 0xffffffff
+#define OCOTP_CRYPTO_BITS_OFFSET 0
+
+#define OCOTP_HWCAP_BITS_MASK 0xffffffff
+#define OCOTP_HWCAP_BITS_OFFSET 0
+
+#define OCOTP_SWCAP_BITS_MASK 0xffffffff
+#define OCOTP_SWCAP_BITS_OFFSET 0
+
+#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2)
+#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1)
+
+#define OCOTP_LOCK_ROM7 (1 << 31)
+#define OCOTP_LOCK_ROM6 (1 << 30)
+#define OCOTP_LOCK_ROM5 (1 << 29)
+#define OCOTP_LOCK_ROM4 (1 << 28)
+#define OCOTP_LOCK_ROM3 (1 << 27)
+#define OCOTP_LOCK_ROM2 (1 << 26)
+#define OCOTP_LOCK_ROM1 (1 << 25)
+#define OCOTP_LOCK_ROM0 (1 << 24)
+#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23)
+#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22)
+#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21)
+#define OCOTP_LOCK_PIN (1 << 20)
+#define OCOTP_LOCK_OPS (1 << 19)
+#define OCOTP_LOCK_UN2 (1 << 18)
+#define OCOTP_LOCK_UN1 (1 << 17)
+#define OCOTP_LOCK_UN0 (1 << 16)
+#define OCOTP_LOCK_SRK (1 << 15)
+#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12)
+#define OCOTP_LOCK_UNALLOCATED_OFFSET 12
+#define OCOTP_LOCK_SRK_SHADOW (1 << 11)
+#define OCOTP_LOCK_ROM_SHADOW (1 << 10)
+#define OCOTP_LOCK_CUSTCAP (1 << 9)
+#define OCOTP_LOCK_HWSW (1 << 8)
+#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7)
+#define OCOTP_LOCK_HWSW_SHADOW (1 << 6)
+#define OCOTP_LOCK_CRYPTODCP (1 << 5)
+#define OCOTP_LOCK_CRYPTOKEY (1 << 4)
+#define OCOTP_LOCK_CUST3 (1 << 3)
+#define OCOTP_LOCK_CUST2 (1 << 2)
+#define OCOTP_LOCK_CUST1 (1 << 1)
+#define OCOTP_LOCK_CUST0 (1 << 0)
+
+#define OCOTP_OPS_BITS_MASK 0xffffffff
+#define OCOTP_OPS_BITS_OFFSET 0
+
+#define OCOTP_UN_BITS_MASK 0xffffffff
+#define OCOTP_UN_BITS_OFFSET 0
+
+#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24)
+#define OCOTP_ROM_BOOT_MODE_OFFSET 24
+#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22)
+#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22
+#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20)
+#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20
+#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14)
+#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14
+#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12)
+#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12
+#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8)
+#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8
+#define OCOTP_ROM_EMMC_USE_DDR (1 << 7)
+#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6)
+#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5)
+#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4)
+#define OCOTP_ROM_SD_MBR_BOOT (1 << 3)
+
+#define OCOTP_SRK_BITS_MASK 0xffffffff
+#define OCOTP_SRK_BITS_OFFSET 0
+
+#define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
+#define OCOTP_VERSION_MAJOR_OFFSET 24
+#define OCOTP_VERSION_MINOR_MASK (0xff << 16)
+#define OCOTP_VERSION_MINOR_OFFSET 16
+#define OCOTP_VERSION_STEP_MASK 0xffff
+#define OCOTP_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_OCOTP_H__ */
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