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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:49 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:14 -0800 |
| commit | b87e6f88e9218da3de371bb6cc8a34924153178e (patch) | |
| tree | fe1c672d5af630646b8c1193b9f00c2132e857f8 /arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | |
| parent | 49fd1f3f265efc00d61effa995bd6a733bf273d8 (diff) | |
| download | talos-obmc-uboot-b87e6f88e9218da3de371bb6cc8a34924153178e.tar.gz talos-obmc-uboot-b87e6f88e9218da3de371bb6cc8a34924153178e.zip | |
armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index ee1d6512d9..dd11ef79c8 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -15,6 +15,7 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_ddrbus2; unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN @@ -60,6 +61,8 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; |
